Dual-Output Shift Register for Narrow Bezel Displays
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Solution Overview
Problem
Existing gate driving circuits in display technology require a large number of shift registers to output gate drive signals to pixels, limiting the development of narrow bezel display devices, as each shift register can only drive a single row of pixels.
Innovation Solution
A shift register design that includes an input circuit, first and second output circuits, pull-down control and reset circuits, allowing for the simultaneous driving of two rows of pixels by utilizing multiple clock signals and power signals to transmit signals effectively across nodes and output terminals, enabling cascaded connection of shift registers to reduce the number of required shift registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If each shift register outputs gate drive signal to only one row of pixels, then the gate driving circuit can be simply designed, but a large number of shift registers are required, increasing device complexity and limiting narrow bezel development
Solution Approach 1:
The shift register is designed with dual output capability, where a single shift register can drive two different rows of pixels simultaneously through first and second output terminals. This multi-functionality reduces the total number of shift registers needed in the gate driving circuit, thereby reducing device complexity while maintaining driving capability for multiple pixel rows
Solution Approach 2:
The patent combines the functionality of multiple shift registers into a single unit by enabling one shift register to output to multiple pixel rows. The first output circuit and second output circuit are merged within the same shift register structure, allowing simultaneous driving of different pixel rows and reducing the overall quantity of shift registers required
2Quantity of substance
If multiple output circuits are added to enable simultaneous driving of two rows of pixels, then the number of shift registers can be reduced, but the device complexity increases
Solution Approach 1:
The shift register is segmented into distinct functional modules: input circuit, first output circuit, second output circuit, pull-down control circuit, and reset circuit. Each module has a specific function, and they are organized in a structured manner. This segmentation allows the complex dual-output functionality to be managed through modular design, reducing the perceived complexity while enabling simultaneous driving of two pixel rows
Solution Approach 2:
The patent adds a dimensional aspect to the shift register output by creating separate output paths (first output terminal and second output terminal) that can drive different pixel rows independently. This dimensional expansion allows a single shift register to serve multiple purposes without requiring a complete redesign of the core shift register functionality
3Reliability
If charging time is increased to minimize edge losses, then signal integrity improves, but the driving speed may be reduced
Solution Approach 1:
The patent employs periodic clock signals (first clock signal, second clock signal, third clock signal) to control the timing of signal transmission through the shift register. By synchronizing the charging and signal transmission operations with periodic clock cycles, the system ensures adequate charging time for signal integrity while maintaining overall driving speed through coordinated periodic operation of multiple circuits
Data Source
AI summary
A shift register includes an input circuit, a first output circuit, a second output circuit, a pull-down control circuit, a pull-down circuit, and a reset circuit. The shift register provided by the disclosure can drive two rows of gate lines.