Dual-Output Shift Register for Compact Scan Driving Circuit

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Solution Overview

Problem

Existing display panels have a relatively large layout space for the scan driving circuit due to the need for multiple shift registers to scan multiple rows of pixels, which hinders the realization of a full screen display.

Innovation Solution

A shift register design that includes an input module, control module, reset module, first output module, second output module, and stabilization module, where the second output module's signal phase lags behind and does not overlap with the first output module's phase, allowing both modules to output signals to two gate lines, reducing the layout area by scanning two rows of pixels with a single shift register.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple shift registers are used to scan multiple rows of pixels, then the pixel array can be fully driven, but the layout space occupied by the scan driving circuit increases

Engineering Contradiction:
Improvepixel scanning capabilityVSAvoidscan driving circuit layout area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The shift register is designed with dual output modules (first output module and second output module) that can simultaneously drive two different gate lines (first gate line and second gate line). This multi-functionality allows a single shift register to perform the work of multiple shift registers, reducing the overall layout area of the scan driving circuit while maintaining the capability to scan multiple rows of pixels

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of stationary object

If a single shift register drives two gate lines simultaneously, then the layout area is reduced, but the signal phase overlap may cause interference

Engineering Contradiction:
Improvescan driving circuit layout areaVSAvoidsignal interference
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent employs phase-sequential clock signals (first clock signal, second clock signal, third clock signal) that are periodically activated in sequence. The control module uses these periodic clock signals to alternately control the first output module and second output module, ensuring that their output phases do not overlap. This periodic action timing mechanism prevents signal interference while enabling dual gate line driving from a single shift register

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20220215791A1Shift register having two output signals with phase lagging and driving method thereof, scan driving circuit, display panel and display device
Publication Date: 2022.07.07 XIAMEN TIANMA MICRO ELECTRONICS
  • US20220215791A1 patent drawing
  • US20220215791A1 patent drawing
  • US20220215791A1 patent drawing

AI summary

The present disclosure provides a shift register and a driving method thereof, a scan driving circuit, a display panel, and a display device. The shift register includes an input module; a control module; a reset module; a first output module; a second output module; and a stabilization module, that a phase of a signal output from the second output module lags behind a phase of a signal output from the first output module, and does not overlap with the phase of the signal output from the first output module.