3D Memory Cell Stack Using Dual Oxide Layers and Metal Word Lines
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Solution Overview
Problem
Current 3D non-volatile memory devices face challenges in achieving high integration density and data retention due to carrier depletion effects in semiconductor materials used for word line layers, which affect electrical resistivity and memory cell performance.
Innovation Solution
The use of metal materials for word line layers, such as Cu, Al, Ti, and Ni, which offer lower electrical resistivity compared to doped semiconductor materials, and a dual oxide semiconductor layer structure with a high-k dielectric layer to improve data retention and stability by reducing carrier depletion effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If doped semiconductor materials are used for word line layers, then the device structure is simpler to manufacture, but carrier depletion effects occur leading to higher electrical resistivity and reduced memory cell performance
Solution Approach 1:
The patent changes the material parameter from doped semiconductor to metal materials (such as Ti, Al, Cu, Ni), fundamentally altering the electrical properties and eliminating carrier depletion effects. This parameter change resolves the contradiction by providing both low electrical resistivity and high reliability without the manufacturing complexity associated with doped semiconductor processing.
Solution Approach 2:
The patent employs a composite structure combining metal word line layers with oxide semiconductor layers (such as IGZO, IZO, GZO). This composite material approach leverages the advantages of both materials: metals provide low electrical resistivity and high conductivity, while oxide semiconductors provide stability and reduced carrier depletion, thereby improving memory cell performance while maintaining manufacturing feasibility.
2Reliability
If metal materials are used for word line layers, then electrical resistivity is reduced improving performance, but manufacturing process complexity increases
Solution Approach 1:
The patent changes the material parameter from doped semiconductor to metal materials (such as Ti, Al, Cu, Ni), fundamentally altering the electrical properties and eliminating carrier depletion effects. This parameter change resolves the contradiction by providing both low electrical resistivity and high reliability without the manufacturing complexity associated with doped semiconductor processing.
Solution Approach 2:
The patent applies metal materials specifically to the word line layer regions where low electrical resistivity is most critical for performance, while using oxide semiconductor materials in other regions. This local quality approach optimizes the balance between manufacturing complexity and performance improvement by applying complex material solutions only where necessary.
3Reliability
If single oxide semiconductor layer is used, then the structure is simpler, but data retention and stability are insufficient due to carrier depletion effects
Solution Approach 1:
The patent employs a composite structure combining metal word line layers with oxide semiconductor layers (such as IGZO, IZO, GZO). This composite material approach leverages the advantages of both materials: metals provide low electrical resistivity and high conductivity, while oxide semiconductors provide stability and reduced carrier depletion, thereby improving memory cell performance while maintaining manufacturing feasibility.
Solution Approach 2:
The patent segments the semiconductor layer into multiple oxide semiconductor layers with different compositions or properties. This segmentation allows each layer to perform specific functions: one layer may provide carrier confinement while another provides stability, collectively improving data retention without requiring excessive structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of metal word line layers and a dual oxide semiconductor layer structure enhances data retention and stability, leading to faster memory device performance and improved integration density in 3D memory devices.
Implementation Method 1
The use of metal materials for word line layers, such as Cu, Al, Ti, and Ni, which offer lower electrical resistivity compared to doped semiconductor materials
Implementation Method 2
a dual oxide semiconductor layer structure with a high-k dielectric layer to improve data retention and stability by reducing carrier depletion effects
Data Source
AI summary
A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.