Dual Signed Unsigned Packed Data Multiplication
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Solution Overview
Problem
Current computer processors lack an efficient method for performing dual signed and unsigned multiplication of packed data elements, requiring sequential instructions that are not optimized for performance.
Innovation Solution
The introduction of vector packed instructions, such as VPMULUDHHQ for unsigned multiplication and VPMULDHHQ for signed multiplication, allows for concurrent multiplication of packed data elements within a single instruction, enhancing processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential multiply instructions are used for signed and unsigned multiplication, then instruction compatibility is maintained, but processing speed and computational throughput deteriorate
Solution Approach 1:
The patent combines signed and unsigned multiplication operations into a single unified instruction (VPMULDD). This instruction can perform both signed and unsigned dual multiplication concurrently, eliminating the need for separate instructions and thereby improving processing speed while reducing instruction overhead.
Solution Approach 2:
The VPMULDD instruction is designed to be universal, handling both signed and unsigned multiplication cases within a single operation. This multi-functional approach allows the processor to execute diverse multiplication tasks without requiring multiple specialized instructions, thus enhancing throughput and reducing computational latency.
2Productivity
If separate instructions are used for signed and unsigned multiplication, then operational precision is maintained, but instruction overhead increases
Solution Approach 1:
By merging signed and unsigned multiplication into the VPMULDD instruction, the patent reduces the number of instructions required in the execution pipeline. This consolidation decreases instruction overhead and improves computational throughput by eliminating redundant instruction fetch, decode, and execution cycles.
Solution Approach 2:
The unified VPMULDD instruction performs preliminary classification of operand types (signed or unsigned) and executes the appropriate multiplication mode in a single operation. This preliminary action eliminates the need for separate instruction sequences, thereby reducing time loss and improving overall productivity.
3Power
If existing SIMD microarchitectures are used, then hardware resource utilization is efficient, but dual multiplication performance deteriorates
Solution Approach 1:
The VPMULDD instruction segments the 128-bit source operands into multiple 32-bit elements, performing dual multiplication operations on each segment concurrently. This segmentation allows the processor to utilize existing SIMD hardware resources efficiently while achieving high-performance dual multiplication through parallel execution of multiple operations.
Data Source
AI summary
An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed doubleword data elements; a second source register to store a second plurality of packed doubleword data elements; and execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to multiply a first doubleword data element from the first source register with a second doubleword data element from the second source register to generate a first quadword product and to concurrently multiply a third doubleword data element from the first source register with a fourth doubleword data element from the second source register to generate a second quadword product; and a destination register to store the first quadword product and the second quadword product as first and second packed quadword data elements.