Dual Panel Pixel Readout Architecture for CMOS Imager Frame Rate
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Solution Overview
Problem
Conventional CMOS imagers face challenges in improving frame rate due to high row processing time, which is not adequately addressed by existing pipelining architectures that increase column complexity and chip area.
Innovation Solution
Implementing a dual panel pixel architecture with separate row decoders and pipelined readout and column readout operations to reduce row processing time without increasing column circuitry complexity, using a shared or non-shared pixel configuration to enhance fill factor and frame rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional single panel pixel readout architecture is used, then column circuitry complexity is maintained at acceptable levels, but row processing time becomes excessively long which limits frame rate
Solution Approach 1:
The pixel array is divided into two separate panels, each with its own row decoder. This segmentation allows parallel processing of different row groups, enabling pipelined operation where one panel is being read out while the other is being processed, thereby reducing overall row processing time and improving frame rate without increasing column circuitry complexity
2Productivity
If pipelining architecture is implemented to reduce row processing time, then frame rate improves, but column circuitry complexity and chip area increase
Solution Approach 1:
By segmenting the pixel array into two panels with separate row decoders, the patent achieves pipelined readout without requiring complex column circuitry modifications. Each panel processes rows independently, allowing overlapping of row processing and column readout operations, thus improving frame rate while maintaining simple column circuitry
Solution Approach 2:
The patent introduces a panel dimension in addition to the traditional row-column structure. This dimensional change enables parallel processing paths where different panels can be processed simultaneously, achieving pipelining效果 without increasing column circuitry complexity since the parallelism is achieved at the panel level rather than the column level
3Productivity
If dual panel architecture with separate row decoders is implemented, then row processing time is reduced and frame rate improves, but device complexity increases
Solution Approach 1:
The pixel array is divided into two separate panels, each with its own row decoder. This segmentation allows parallel processing of different row groups, enabling pipelined operation where one panel is being read out while the other is being processed, thereby reducing overall row processing time and improving frame rate without increasing column circuitry complexity
Solution Approach 2:
The patent uses identical row decoder circuits for both panels, copying the same design twice. This approach simplifies the overall system because the decoder logic remains unchanged and can be replicated easily, reducing design complexity while achieving parallel processing capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual panel architecture significantly reduces row processing time, thereby improving the frame rate of CMOS imagers while maintaining improved fill factor without increasing column circuitry complexity or chip area.
Implementation Method 1
each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate
Data Source
AI summary
An imager having two panels of pixels (i.e., the imager's rows of pixels are split into two panels) that are controllable by separate row decoders. The dual panel architecture allows pipelining of pixel readout and column readout operations to improve the imager's frame rate. The dual panel architecture may use a standard pixel configuration, a shared column and/or a shared row and column configuration.