Dual Passivation Stack for Interline Dielectric Protection
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Solution Overview
Problem
Premature breakdown of interline dielectric regions in integrated circuits due to moisture ingress and electrical conduction assisted by defects, particularly in advanced CMOS technologies, where existing non-porous dielectric barriers like TEOS oxide are not impermeable to moisture, allowing leakage currents.
Innovation Solution
A dual passivation stack comprising a non-porous lower passivation layer, an electrically insulating layer, and an upper passivation layer, with the lower passivation layer being locally etched to reveal contact pads, using materials like silicon nitride to prevent moisture ingress and protect against dielectric breakdown, while being compatible with CMOS methods and existing non-porous dielectric barrier solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a non-porous dielectric barrier like TEOS oxide is used to protect against Poole-Frenkel conduction, then electrical breakdown protection is improved, but moisture impermeability deteriorates allowing leakage currents
Solution Approach 1:
The patent applies composite materials by combining TEOS oxide layer with silicon nitride (Si3N4) layer to create a multi-layer dielectric barrier structure. The TEOS oxide provides electrical breakdown protection while the silicon nitride layer provides moisture impermeability, thus resolving the contradiction between electrical protection and moisture barrier properties
Solution Approach 2:
The patent applies local quality by depositing the silicon nitride layer selectively in specific regions where moisture ingress is most critical, such as along the sidewalls of through-silicon vias (TSVs) and in interconnect regions, while maintaining the TEOS oxide structure elsewhere for electrical protection
2Ease of manufacture
If porous dielectric regions are used in interconnection parts, then manufacturing flexibility is improved, but susceptibility to moisture ingress and breakdown increases
Solution Approach 1:
The patent applies local quality by maintaining porous dielectric regions in areas where manufacturing flexibility is needed while applying non-porous dielectric barriers (TEOS oxide and silicon nitride) in areas where moisture resistance is critical, such as along TSV sidewalls and in high-stress interconnect regions
Solution Approach 2:
The patent combines porous dielectric materials with non-porous dielectric barrier layers to create a composite structure that retains the manufacturing advantages of porous materials while adding the moisture resistance properties of non-porous materials through the multi-layer barrier system
3Productivity
If advanced CMOS technological nodes are used to reduce minimum distance between lines, then integration density is improved, but risk of premature breakdown increases
Solution Approach 1:
The patent applies composite materials by implementing a multi-layer dielectric barrier structure (TEOS oxide combined with silicon nitride) that provides enhanced protection against premature breakdown, enabling the use of advanced CMOS nodes with reduced line spacing while maintaining reliability
Solution Approach 2:
The patent applies beforehand cushioning by depositing the dielectric barrier layers (TEOS oxide and silicon nitride) in advance during the fabrication process, before the interconnect structures are fully assembled and before moisture ingress or electrical stress can cause breakdown, thus preemptively protecting the structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces the risk of premature dielectric breakdown by impeding moisture ingress and blocking leakage currents, ensuring effective protection of interline dielectric regions without requiring mask modifications or additional layout changes.
Implementation Method 1
a non-porous lower passivation layer... to prevent moisture ingress
Implementation Method 2
the electrons then propagate by jumps between states located in the forbidden band of the dielectric which are assumed to be ionized centers (donors of electrons). This effect results from the lowering of the energy of ionization of these centers with the application of an electric field
Data Source
AI summary
A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.