Dual-Path Floating-Point Adder for Subnormal Number Support
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional digital signal processing (DSP) blocks in programmable logic devices (PLDs) lack support for subnormal numbers in floating-point arithmetic, limiting their ability to handle small floating-point numbers effectively.
Innovation Solution
The integration of a dual-path floating-point adder architecture that includes near-path and far-path circuits, capable of handling both normal and subnormal numbers by splitting inputs based on exponent differences and performing appropriate arithmetic and normalization operations to support subnormal number processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional floating-point adder architecture is used, then the circuit is simple and fast, but it cannot handle subnormal numbers effectively
Solution Approach 1:
The adder is divided into two separate paths: a near-path for normal floating-point numbers and a far-path for subnormal numbers. The near-path handles standard operations efficiently, while the far-path performs denormalization, arithmetic, and normalization specifically for subnormal inputs. This segmentation allows the circuit to support subnormal numbers without compromising the performance of normal number operations.
Solution Approach 2:
The circuit dynamically selects between near-path and far-path based on the exponent values of the input operands. When both operands are normal, the near-path is used for fast computation. When subnormal numbers are detected (through exponent comparison), the far-path is activated. This dynamic switching optimizes performance by using the appropriate path for each operation type.
2Measurement precision
If dual-path architecture with subnormal support is implemented, then subnormal number handling is accurate, but circuit complexity increases
Solution Approach 1:
Different parts of the circuit are optimized for different functions: the near-path is optimized for speed and simplicity in handling normal numbers, while the far-path is specifically designed with denormalization logic, arithmetic units, and normalization logic to ensure high precision for subnormal numbers. Each path has the exact complexity needed for its specific purpose.
Solution Approach 2:
The far-path acts as an intermediary between subnormal number inputs and the final result. It receives subnormal operands, denormalizes them to a common exponent format, performs the arithmetic operation, and then normalizes the result before outputting to the near-path or directly to the result register. This intermediary structure ensures accurate subnormal processing without affecting the main arithmetic path.
3Adaptability or versatility
If exponent comparison and path selection logic is added, then subnormal support is enabled, but processing time increases
Solution Approach 1:
The circuit performs preliminary exponent comparison and path selection at the beginning of the arithmetic operation, before the actual addition or subtraction takes place. By detecting whether operands are normal or subnormal early in the process, the circuit can immediately route to the appropriate path without delays during or after the computation.
Solution Approach 2:
Both near-path and far-path operate in parallel with continuous data flow. The path selection logic continuously monitors exponent values and switches between paths without interrupting the arithmetic operation. Once a path is selected, the computation proceeds continuously through to completion, minimizing any time loss from the added complexity.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An integrated circuit may include a floating-point adder. The adder may be implemented using a dual-path adder architecture having a near path and a far path. The near path may include a leading zero anticipator (LZA), a comparison circuit for comparing an exponent value to an LZA count, and associated circuitry for handling subnormal numbers. The far path may include a subtraction circuit for computing the difference between a received exponent value and a minimum exponent value, at least two shifters for shifting far greater and far lesser mantissa values in parallel, and associated circuitry for handling subnormal numbers. The adder may be dynamically configured to support a first mode that processes FP16 at inputs and outputs, a second mode that processes modified FP16' inputs, and a third mode that processes FP16' at inputs and outputs.