Dual-Path Clock Recovery for Wide Pull-In and Jitter Tolerance
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Solution Overview
Problem
Existing clock and data recovery circuits operate at wider bandwidths than necessary, leading to limitations in high-frequency jitter tolerance and slow locking to incoming data rates, due to stringent pull-in range requirements in standards like DisplayPort, USB 3.0, and SATA.
Innovation Solution
A dual-path integrated circuit design with a first branch for clock signal recovery and a second branch for data signal recovery, where the clock branch has infinite pull-in bandwidth and optimizes the data branch's bandwidth for the expected frequency range, allowing the data branch to lock quickly to the incoming data signal once the clock signal is locked.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the bandwidth is made wide enough to fulfill the pull-in range requirement, then the receiver can lock to incoming signals in the specified frequency range, but the receiver operates at much wider bandwidth than required which limits high frequency jitter tolerance
Solution Approach 1:
The receiver is divided into two separate branches: a first branch dedicated to clock signal recovery with wide bandwidth for pull-in, and a second branch for data signal recovery with optimized narrower bandwidth. This segmentation allows each branch to be optimized for its specific function, resolving the contradiction between wide bandwidth needs for locking and narrow bandwidth needs for jitter tolerance.
Solution Approach 2:
The system dynamically transfers control from the first branch to the second branch once locking is achieved. The second branch is enabled to take over data recovery operations, allowing the effective bandwidth to be reduced after the initial locking phase, thereby improving high-frequency jitter tolerance while maintaining the ability to lock onto incoming signals.
2Speed
If the bandwidth is made wide to ensure tracking capability, then the receiver can track specified input jitter, but the design is constrained by the more stringent pull-in range requirement
Solution Approach 1:
The receiver functionality is segmented into two specialized branches, allowing the first branch to be optimized for wide bandwidth and jitter tracking, while the second branch handles data recovery with appropriate bandwidth. This eliminates the need for a single over-provisioned bandwidth design.
Solution Approach 2:
The first branch temporarily operates with excessive bandwidth capability to ensure reliable locking and jitter tracking during the critical acquisition phase, but this excessive bandwidth is not continuously required once the second branch takes over data recovery operations.
3Device complexity
If a single branch is used for both clock and data recovery, then the design is simpler, but the bandwidth must be wide enough for pull-in which limits jitter tolerance
Solution Approach 1:
The receiver is segmented into two functional branches with distinct optimization goals. The first branch specializes in clock recovery with wide bandwidth for pull-in, while the second branch specializes in data recovery with optimized bandwidth for jitter tolerance. This segmentation resolves the contradiction between structural simplicity and performance optimization.
Solution Approach 2:
Both branches process input signals and can perform recovery functions, providing functional redundancy and versatility. The system can operate with either branch depending on the operational phase, making the overall system more robust while allowing each individual branch to be optimized for its primary function.
Data Source
AI summary
A device and method for clock and data recovery are disclosed. For example, an integrated circuit comprises a first branch for recovering a clock signal from an input signal. The first branch includes a phase and frequency detector for detecting a phase and a frequency of the clock signal and a numerically controlled oscillator that is controlled by the phase and the frequency of the clock signal from the phase and frequency detector. The integrated circuit also includes a second branch for recovering a data signal from the input signal. The second branch includes a pre-settable numerically controlled oscillator that is pre-settable with the phase and the frequency of the clock signal from the numerically controlled oscillator. The second branch also includes a sample selector that is controlled by the pre-settable numerically controlled oscillator for recovering the data signal.