Dual-Path Digital-to-Time Converter for Spur-Resistant Phase Detection
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Solution Overview
Problem
Digital phase-locked loops (DPLLs) face issues with quantization noise and non-linearity, particularly when operating near-integer channels, leading to spurious tone generation due to the limited resolution and non-linearity of conventional digital-to-time converters (DTCs), which complicates calibration and increases power consumption.
Innovation Solution
A dual-path digital-to-time converter (DTC) with a delay chain circuit and a dynamic element matching (DEM) controller is introduced, providing a fast and slow path with digitally controlled delays, reducing code-dependent non-linearity and power supply noise effects by applying relative delays to both input signals, thus improving phase detection accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional single-path DTC is used to improve phase detection resolution, then measurement precision is improved, but device complexity and power consumption increase due to complex calibration logic
Solution Approach 1:
The delay chain is segmented into multiple individually controllable delay cells, each receiving independent control signals from the DEM controller. This segmentation allows for granular adjustment of delay amounts and enables the complex calibration to be distributed across multiple simple, identical units rather than requiring complex logic in a single component.
Solution Approach 2:
The invention changes the control parameter from a single complex calibration value to multiple independent delay control signals. By controlling each delay cell with separate signals, the system can achieve fine-grained phase adjustment while using simpler, more modular control logic that is easier to calibrate and less prone to cumulative errors.
2Measurement precision
If a conventional single-path DTC is used to improve phase detection accuracy, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The delay chain is divided into multiple independent delay cells that can be controlled individually. This segmentation allows the system to achieve high phase detection accuracy through fine-grained control while managing power consumption by activating only the necessary delay cells rather than requiring all cells to operate at full precision simultaneously.
Solution Approach 2:
Multiple identical delay cells are used instead of a single complex delay element. Each cell is a simplified copy of the others, allowing the system to achieve the required total delay and precision through parallel simple units rather than a single power-hungry complex unit, thereby reducing overall power consumption while maintaining accuracy.
3Adaptability or versatility
If fractional operation is implemented in DPLL to relax system planning constraints, then adaptability is improved, but spurious tone generation increases due to quantization noise and non-linearity
Solution Approach 1:
The delay amount in each delay cell is dynamically adjustable through independent control signals from the DEM controller. This dynamic control allows the system to continuously adjust the phase delay to achieve precise fractional-N operation, reducing quantization noise and non-linearity effects that cause spurious tones, while maintaining the adaptability needed for relaxed system planning.
4Measurement precision
If a conventional DTC applies delay to only one signal to improve phase detection, then measurement precision is improved, but reliability decreases due to susceptibility to power supply noise and dynamic mismatches
Solution Approach 1:
The invention merges the delay functionality into a dual-path structure where both the reference clock signal and the synthesized clock signal pass through identical delay chains. This merging of delay operations into symmetric paths ensures that both signals experience the same delays and are equally susceptible to the same noise and mismatches, which cancel out in the phase comparison, thereby improving reliability while maintaining precision.
Data Source
AI summary
An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.