Dual-Path Delay Circuit for Independent Edge Timing Control

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Solution Overview

Problem

Conventional delay circuits cannot separately adjust the delay time of rising and falling edges of a signal, limiting their ability to precisely control signal propagation.

Innovation Solution

A delay circuit comprising a first and second delay line, a control circuit, and logic circuits that allow for distinct delay times for rising and falling edges, with the control circuit generating a control signal to manage the output signals from the logic circuits, ensuring they do not output simultaneously and allowing for different lengths of delay times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional delay circuit uses a single delay path with PMOS and NMOS transistors, then the circuit structure is simple, but the delay time of rising and falling edges cannot be separately adjusted

Engineering Contradiction:
Improveseparate adjustment of rising and falling edge delay timesVSAvoidcircuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The delay circuit is divided into two separate delay paths: a first delay path for delaying the rising edge and a second delay path for delaying the falling edge. Each path has its own delay element and control mechanism, allowing independent adjustment of delay times for rising and falling edges without increasing overall circuit complexity significantly

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit uses control signals that can dynamically switch between different delay configurations. The control circuit generates control signals that enable selective activation of different delay paths based on the signal edge type (rising or falling), providing dynamic adaptability while maintaining a relatively simple static structure

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If the delay circuit uses separate delay paths for rising and falling edges, then the delay time control precision is improved, but the circuit complexity increases

Engineering Contradiction:
Improvedelay time control precisionVSAvoidnumber of delay elements and control circuits
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The delay elements and control circuits are designed to serve multiple functions. The same types of components (delay elements, control circuits, logic gates) are reused in both delay paths, reducing the overall component count and complexity while achieving precise separate control of rising and falling edge delays

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The circuit achieves precise delay control by changing parameters of existing components rather than adding numerous components. The delay times are adjusted by modifying the delay characteristics of delay elements through control signals, allowing precise control without proportionally increasing circuit complexity

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If the logic circuits output signals simultaneously, then the circuit operation is simple, but the signal propagation control is poor

Engineering Contradiction:
Improvesignal propagation controlVSAvoidcontrol circuit for managing output signals
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

A control circuit acts as an intermediary between the delay paths and the final output. This control circuit receives control signals and manages the timing of output signals from the first and second logic circuits, ensuring they do not output simultaneously. The intermediary control circuit adds minimal complexity while significantly improving signal propagation control

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7605630B2Delay circuit
Publication Date: 2009.10.20 NAN YA TECH
  • US7605630B2 patent drawing
  • US7605630B2 patent drawing
  • US7605630B2 patent drawing

AI summary

A delay circuit respectively delays rising and falling edges of an input signal. The delay circuit comprises first and second delay lines, a control circuit, and first and second logic circuits. The first delay line delays the first input signal the first delay time to output the first delay output signal. The second delay line delays the first input signal the second delay time to output the second delay output signal. The control circuit outputs the control signal according to the first input signal. The first logic circuit receives the first delay output signal and outputs the first output signal according to the control signal and the first input signal. The second logic circuit receives the second delay output signal and outputs the second output signal according to the control signal and the first input signal. The first and second delay times are different.