Dual-Path Level Shifter for Speed, Power, and Noise Immunity

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Solution Overview

Problem

Existing level shifters in wireless communication networks face challenges in achieving low power consumption while maintaining high speed and noise immunity, often requiring trade-offs between these parameters.

Innovation Solution

A level-shifting circuit design that incorporates a fast circuit path and a pulse generator to detect signal transitions, momentarily turning on a fast circuit path for high-speed transitions and using a slow circuit path in parallel to ensure accurate state maintenance and noise resistance, employing differential transistors and current-limiting circuits to manage power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a fast circuit path is used for high-speed transitions, then speed is improved, but power consumption increases

Engineering Contradiction:
Improvetransition speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The circuit dynamically switches between a fast circuit path and a slow circuit path based on operational needs. The fast path is activated only during signal transitions for high-speed operation, while the slow path handles steady-state operations with lower power consumption, making the system's characteristics changeable rather than fixed

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The circuit uses periodic pulsing to activate the fast circuit path only when needed for transitions, rather than keeping it continuously active. This pulsed operation allows the fast path to provide high-speed performance when required while remaining inactive during steady states, thereby reducing overall power consumption

Inventive Principle:
Principle #19Periodic action

2Reliability

If noise immunity is improved through filtering, then reliability is improved, but speed deteriorates

Engineering Contradiction:
Improvenoise immunityVSAvoidresponse speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The circuit is segmented into two separate paths: a fast path for high-speed signal transitions and a slow path for noise-immune steady-state operations. By dividing the circuit functionality, each path can be optimized for its specific purpose without compromising the other, allowing the system to achieve both speed and noise immunity at different times

Inventive Principle:
Principle #1Segmentation

3Use of energy by moving object

If power consumption is reduced, then energy efficiency is improved, but speed deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidtransition speed
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The circuit dynamically adjusts its operational mode by switching between fast and slow paths based on whether transitions are needed. During transitions, the fast path provides high-speed operation; during steady states, the slow path provides low-power operation. This dynamic adaptation resolves the contradiction by making speed available when needed while minimizing power consumption during normal operation

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10615796B2Level shifter
Publication Date: 2020.04.07 QUALCOMM INC
  • US10615796B2 patent drawing
  • US10615796B2 patent drawing
  • US10615796B2 patent drawing

AI summary

Certain aspects of the present disclosure provide methods and apparatus for level shifting an input signal ranging between certain voltage levels to generate an output signal ranging between other voltage levels with low power, high speed, and immunity to noise. One example level-shifting circuit generally includes a node for receiving an input signal ranging between a first voltage level and a second voltage level, a first circuit path coupled to the node and configured to level shift the input signal to generate an output signal ranging between a third voltage level and a fourth voltage level, a pulse generator coupled to the node and configured to generate a pulse based on a transition in the input signal between the first and second voltage levels, and a second circuit path connected in parallel with the first path and configured to temporarily short the first path based on the generated pulse.