Dual-Path Radiation-Hardened Logic for SET Pulse Suppression
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Solution Overview
Problem
Logic circuits in harsh radiation environments, such as outer space, face functional failures due to Single Event Transients (SETs) caused by energetic heavy ions, and existing solutions like Triple Mode Redundancy increase integrated circuit die area and cost.
Innovation Solution
A radiation-hardened logic circuit design that uses two substantially similar logic paths with an exclusive-OR gate and gating circuitry to attenuate or remove radiation-induced pulses, reducing the need for one layer of redundancy and minimizing integrated circuit die area by at least 33% compared to TMR approaches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Triple Mode Redundancy (TMR) is used to protect against SET-induced pulses, then circuit reliability in radiation environments is improved, but integrated circuit die area increases by triple or more
Solution Approach 1:
The patent extracts and eliminates one layer of redundancy from the traditional TMR architecture, transitioning from triple redundancy to dual redundancy. By removing one redundant logic path while retaining the essential error detection and correction capabilities through modified voting circuitry, the design achieves radiation hardening with reduced die area.
Solution Approach 2:
The patent changes the redundancy parameter from triple (3) to dual (2) while compensating through modified circuit logic and voting mechanisms. This parameter change reduces the number of logic paths from three to two, directly decreasing the integrated circuit die area while maintaining adequate protection against SET-induced pulses through enhanced detection logic.
2Reliability
If Triple Mode Redundancy (TMR) is implemented to eliminate radiation-induced pulses, then circuit performance in high-radiation environments is improved, but device complexity increases
Solution Approach 1:
The patent removes one redundant logic path and associated voting circuitry from the TMR architecture, simplifying the overall device structure. By extracting the unnecessary third redundant path, the design reduces gate count, interconnect complexity, and overall device complexity while preserving the core functionality of detecting and correcting radiation-induced errors.
Solution Approach 2:
Instead of adding more redundancy to improve reliability, the patent inverts the approach by reducing redundancy from triple to dual and compensating through smarter, more efficient voting and detection logic. This inversion achieves comparable or superior reliability with reduced complexity by being more selective about where redundancy is applied.
Data Source
AI summary
A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitry can be a controlled pass-gate circuit and a data latch, an adjustable threshold comparator, or two controlled latches. Transient pulse suppression is achieved with less circuitry and expense than is found in TMR circuits.