Dual-Path PLL Circuit With Boost Control for Fast Locking

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Solution Overview

Problem

Existing phase-locked loop (PLL) circuits, such as those in the AD9173 DAC, suffer from high settling times and increased phase noise due to limited bandwidth, which is problematic for applications requiring fast frequency changes and stability, especially in vector network analyzers.

Innovation Solution

A PLL circuit with a variable frequency oscillator and a dual-filter loop configuration, where a boost circuit is added to the second filter path to provide additional voltage signals in response to error signals, allowing for reduced settling times while maintaining low phase noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the loop bandwidth is increased to decrease settling times, then the settling time is reduced, but the phase noise increases undesirably

Engineering Contradiction:

Improvesettling timeVSAvoidphase noise

Core Design Contradiction:

Loss of timeVSObject-generated harmful factors

Solution Approach 1:

The loop filter is divided into two separate filter paths: a first filter path with higher bandwidth for fast settling and a second filter path with lower bandwidth for low phase noise. Each path processes the control signal independently and their outputs are combined to drive the VCO, allowing simultaneous optimization of both settling time and phase noise performance

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention transitions from a single-dimensional loop filter design to a two-dimensional dual-path architecture. The first path operates in a high-bandwidth dimension for rapid response, while the second path operates in a low-bandwidth dimension for noise filtering, effectively adding a dimensional aspect to the filter design space

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If the tuning range of the loop filter is increased to cover wide frequency ranges, then the frequency range is extended, but the stability of the PLL deteriorates

Engineering Contradiction:

Improvefrequency rangeVSAvoidPLL stability

Core Design Contradiction:

Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The frequency tuning function is segmented between two filter paths: the first filter path handles fine frequency adjustments with high bandwidth for stability, while the second filter path provides coarse frequency adjustments with low bandwidth to prevent instability, allowing the PLL to operate stably across a wide frequency range

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The dual-filter path architecture dynamically adapts to different frequency ranges by utilizing the appropriate filter path based on the required tuning range, enabling the PLL to maintain optimal stability characteristics across varying operating conditions

Inventive Principle:

Principle #15Dynamics

Data Source

PatentEP4266583A1Phase locked loop circuit, electronic circuit arrangement and electronic apparatus

Publication Date: 2023.10.25 ROHDE & SCHWARZ GMBH & CO KG

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AI summary

The present invention relates to a phase-locked loop (PLL) circuit which comprises a variable frequency oscillator, loop filter having a first fine filter path and a second coarse filter path and a boost circuit. According to the invention, the boost circuit is configured to provide at least one additional boost voltage signal to the output signal of the second filter path as a predetermined control signal activates the boost circuit. The invention further relates to an electronic circuit arrangement comprising such a phase locked loop circuit and an electronic apparatus.