Dual-Path PLL Circuit for Low Jitter and High PSRR
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in achieving low jitter, low power consumption, small area occupancy, wide operating range, and immunity to process, voltage, and temperature variations while maintaining a high power supply rejection ratio.
Innovation Solution
The proposed phase-locked loop circuit incorporates an oscillator, a detection block, an integral path, and a proportional path, where the detection block generates both integral and proportional signals to regulate the oscillator's power supply and control terminal, respectively, allowing for frequency control and improved power supply rejection ratio through a feedback loop with an error amplifier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PLL uses a single control path for frequency regulation, then the circuit complexity is low, but the power supply rejection ratio and jitter performance are insufficient
Solution Approach 1:
The control path is segmented into two independent paths: integral path for long-term frequency accuracy and proportional path for short-term jitter suppression. Each path processes control signals differently, allowing optimized performance for each function without compromising the other.
Solution Approach 2:
A dual-path control structure acts as an intermediary between the phase detector and VCO, where the integral path provides DC offset correction and the proportional path provides dynamic jitter suppression, together achieving superior power supply rejection ratio.
2Reliability
If the PLL increases power consumption to reduce jitter, then jitter performance improves, but power consumption increases
Solution Approach 1:
The system dynamically adjusts control parameters through two paths: the integral path adjusts DC control voltage for frequency accuracy, while the proportional path adjusts AC control signals for jitter suppression, optimizing performance without excessive power consumption.
Solution Approach 2:
The proportional path applies partial correction only when phase error occurs, rather than continuous full-power operation, reducing average power consumption while maintaining jitter performance during transient conditions.
3Adaptability or versatility
If the PLL uses analog control signals for frequency regulation, then the operating range is continuous, but immunity to process, voltage, and temperature variations decreases
Solution Approach 1:
The integral path implements feedback control that continuously monitors and corrects for PVT variations, adjusting the DC control voltage to maintain accurate frequency operation across varying process, voltage, and temperature conditions.
Solution Approach 2:
The system changes control parameters dynamically: the integral path modifies DC voltage to compensate for PVT drift, while the proportional path adjusts AC control amplitude and frequency to maintain stability across different operating conditions.
4Area of stationary object
If the PLL reduces area occupancy by integrating components, then area efficiency improves, but the ability to maintain phase lock under varying conditions deteriorates
Solution Approach 1:
The integral and proportional control paths are merged into a unified dual-path architecture that shares common components such as the phase detector and VCO, reducing overall area occupancy while maintaining the functional independence needed for stable phase locking under varying conditions.
Data Source
AI summary
A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal.