Dual-Path PLL Jitter Removal for Gapped Clock Signals
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Solution Overview
Problem
Existing systems that use gapped clocks to align input and output data rates in optical transport networks suffer from unpredictable gap patterns, leading to unguaranteed system performance, excessive latency, and increased costs due to the need for low bandwidth jitter cleaning devices, which are sensitive to temperature fluctuations and ineffective in filtering systematic jitter.
Innovation Solution
A phase-locked loop system that includes a digital phase detector and gap detector to identify and digitally filter out systematic jitter by subtracting a gap value from the phase difference, allowing for separate filtering of thermal and systematic jitter, and using a programmable gap detector to adjust for varying gap patterns, thereby reducing jitter impact and increasing PLL bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If very low bandwidth jitter cleaning devices are used to filter out jitter caused by clock gaps, then the jitter for downstream systems is reduced, but the system response latency becomes excessive and the devices become sensitive to temperature fluctuations
Solution Approach 1:
The jitter cleaning function is segmented into two distinct paths: a first path handling jitter below a predetermined threshold and a second path handling jitter above the threshold. This segmentation allows each path to be optimized for its specific function, with the first path providing low-latency response and the second path providing robust filtering for large systematic jitter.
Solution Approach 2:
The system dynamically changes the bandwidth parameter of the jitter cleaning function by selecting between two different paths based on the jitter magnitude. When jitter is small, a higher bandwidth path is used for fast response; when jitter is large, a lower bandwidth path is used for effective filtering, thus adapting the system behavior to conditions rather than being constrained to a fixed bandwidth.
2Ease of manufacture
If gapped clock techniques are used to align input and output data rates, then system partitioning is simplified, but the gap patterns become unpredictable and difficult to model, preventing performance guarantees
Solution Approach 1:
The system adapts its jitter cleaning bandwidth parameter based on the detected gap patterns in the clock signal. By monitoring the actual gap occurrences and adjusting the cleaning path selection accordingly, the system can provide performance guarantees despite the unpredictable nature of gap patterns inserted by OTN mappers.
3Reliability
If low bandwidth jitter cleaning is used to filter systematic jitter, then jitter is reduced, but the system cost increases due to the need for specialized low bandwidth devices
Solution Approach 1:
The jitter cleaning function is segmented into two distinct paths: a first path handling jitter below a predetermined threshold and a second path handling jitter above the threshold. This segmentation allows each path to be optimized for its specific function, with the first path providing low-latency response and the second path providing robust filtering for large systematic jitter.
Solution Approach 2:
Instead of using expensive, specialized low bandwidth jitter cleaning devices for all conditions, the system uses a dual-path approach where a simpler, faster path handles the majority of small jitter cases, and a more robust but slower path is only activated when needed for large systematic jitter. This reduces overall system cost by avoiding the need for expensive specialized hardware in all operating conditions.
Data Source
AI summary
A gap detector detects when a phase difference between a feedback signal and a clock signal is larger than a gap threshold. If the phase difference is larger than the gap threshold, then the phase difference is modified by subtracting a gap value from the phase difference. If the phase difference is less than the threshold, the phase difference is not modified. A loop filter receives and filters the modified or unmodified phase difference and controls an oscillator. An accumulator circuit accumulates the modified phase difference and supplies a phase adjust signal. A low pass filter receives the phase adjust signal and supplies a filtered phase adjust signal that is used to slowly adjust the output of the oscillator.