Dual-Path Reset Circuit for Clock-Loss Safe RAM Protection
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Solution Overview
Problem
Existing electronic circuits face challenges in providing a reliable reset signal, especially in safety-critical systems where the system clock may not be running, leading to issues with synchronous and asynchronous resets, and potential data loss or corruption in RAM devices.
Innovation Solution
An electronic circuit with a synchronization unit and clock monitoring signal that provides a synchronous reset when the clock is available and an asynchronous reset when it is not, using a dual-path reset signal system with a selection circuit to ensure robust resets without jeopardizing setup and hold times of RAM devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronous reset signal path is used when the clock is available, then the reset is synchronized with the clock signal, but if the clock signal is not available, the reset cannot be properly synchronized leading to potential data loss or corruption
Solution Approach 1:
The reset circuit dynamically switches between synchronous and asynchronous reset modes based on clock availability. A clock monitoring unit detects whether the clock signal is present and controls a selection circuit to choose the appropriate reset path, making the system adaptive to changing operational conditions
Solution Approach 2:
A clock monitoring unit acts as an intermediary between the clock signal and the reset circuitry. It monitors clock availability and generates a control signal that determines whether the synchronous or asynchronous reset path is activated, mediating the interaction between clock status and reset mode
2Adaptability or versatility
If an asynchronous reset path is used when the clock is not available, then the reset can be initiated, but additional wiring and design constraints are required
Solution Approach 1:
The circuit merges the synchronous and asynchronous reset paths into a unified reset output. The selection circuit combines both paths and their control logic into a single integrated structure that produces one reset signal, reducing the need for separate wiring for different reset modes
Solution Approach 2:
The reset circuit is designed with multi-functionality to handle both synchronous and asynchronous reset operations through a single unified structure. The same circuit infrastructure supports both reset modes by switching between them based on clock availability, eliminating the need for dedicated separate reset paths
3Reliability
If a dual-path reset signal system is used to ensure robust resets, then reset reliability is improved, but the device complexity increases
Solution Approach 1:
The reset circuit is segmented into distinct functional modules: a synchronous reset path, an asynchronous reset path, a clock monitoring unit, and a selection circuit. This segmentation allows each component to perform its specific function independently while working together as an integrated system, managing complexity through modular organization
Data Source
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AI summary
An electronic circuit (10) comprises a reset input (12) for receiving an input reset signal, a clock input (14) for receiving a clock signal, and a reset output (16) for providing an output reset signal. And it comprises a synchronous reset signal path (18, 20, 22, 24, 26) comprising a synchronization unit (20, 24), arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path (28, 30, 32) arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal (34) indicates that the clock signal is not available.