Dual Path Resistance Detection for RTD in Disk Drives
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Solution Overview
Problem
Current disk drive technologies are limited by single path monitoring in dual mode resistance detection, which is time-consuming and inefficient, especially during HDD manufacturing and testing, as they can only operate in either alternating current (AC) or direct current (DC) modes simultaneously.
Innovation Solution
A continuous dual path resistance detection architecture that concurrently operates in both AC and DC modes, utilizing a resistance detection circuit with low frequency and high frequency paths, and processing devices to bias resistances, generate signals, and demodulate chopped signals for real-time fly-height monitoring and defect scanning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If single path monitoring is used in dual mode resistance detection, then device complexity is reduced, but productivity deteriorates due to time-consuming sequential operation in AC or DC modes
Solution Approach 1:
The resistance detection circuit is segmented into two independent paths: a first path for AC mode operation and a second path for DC mode operation. Each path has its own amplifier circuit and signal processing chain, allowing simultaneous execution of both AC and DC measurements without interference, thereby reducing total test time while maintaining manageable complexity through modular design
Solution Approach 2:
The resistance detection circuit is designed with multi-functionality to support both AC and DC modes through a unified architecture. The circuit can operate in AC mode for defect scanning, DC mode for fly-height monitoring, or both modes simultaneously via the dual path configuration, making the system versatile and adaptable to different operational requirements without requiring separate dedicated circuits
2Measurement precision
If averaging numerous measurement values is performed to extract DC/LF resistance value, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The DC mode path continuously measures resistance values without interruption, and the processing device continuously averages incoming measurement values in real-time. This continuous averaging process maintains measurement precision while eliminating the need for lengthy batch processing, as the accurate DC resistance value is obtained through ongoing accumulation and averaging of measurements during normal operation
Solution Approach 2:
The system performs preliminary averaging of measurement values as they are acquired, rather than waiting to collect a large batch of data before processing. This preliminary action of continuously averaging incoming data points maintains measurement precision while significantly reducing the time delay associated with post-acquisition batch processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces test time for HDDs by up to several hours, enhances noise reduction, and minimizes offset, allowing for more accurate fly-height control and defect identification.
Implementation Method 1
measuring the resistance of a resistive temperature detector (RTD), such as a resistance of an embedded contact sensor (ECS) resistance or a nearfield temperature sensor (NTS)
Implementation Method 2
chop, on the LF path, a LF signal at the first amplifier circuit at a first clock frequency; and demodulate the chopped LF signal on the LF path using the first clock frequency to generate a LF resistance detection signal
Implementation Method 3
add a bias pulse on the HF path to generate a HF resistance detection signal, where the second amplifier circuit is biased using the voltage bias and the bias pulse
Data Source
AI summary
Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector with a first resistance, a resistance detection circuit electrically coupled to the first resistance and comprising a low and high frequency path corresponding to a DC and AC mode, respectively, and one or more processing devices configured to: bias the first resistance with a voltage bias, where the first resistance is coupled to a first and second amplifier, control a pulse generator to add a bias pulse on the HF path to generate a HF resistance detection signal, where the second amplifier is biased using the voltage bias and the bias pulse, control a clock to chop a LF signal at the first amplifier on the LF path, demodulate the chopped LF signal to generate a LF resistance detection signal, and concurrently process the HF and LF resistance detection signals.