Dual-Path Clock Forwarding for Low-Jitter Retimer Transmit Clocks
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Solution Overview
Problem
Jitter in the receive clock causes undesirable jitter in the retransmission clock, impairing system performance, particularly due to process, voltage, and temperature variations in existing digital retimers.
Innovation Solution
Implementing a dual path clock forwarding mechanism in retimers that includes a sampling element, timing error estimator, clock recovery circuit, and transmit clock generator to derive the transmit clock based on a reference clock, frequency signal, and phase error, using phase and frequency filters to minimize jitter impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the retransmission clock is tied directly or indirectly to the recovered receive clock, then the retimer can perform clock recovery and retransmission, but jitter in the receive clock causes jitter in the retransmission clock, impairing system performance
Solution Approach 1:
The patent segments the clock signal path into two independent paths: a primary path using the recovered receive clock and a secondary path using an independent reference clock. This segmentation allows the system to bypass jitter propagation by switching to the clean reference clock path when needed, resolving the contradiction between maintaining clock synchronization and eliminating jitter.
Solution Approach 2:
The patent introduces a jitter filter as an intermediary component that processes the transmit clock signal. This filter acts as a mediator between the jittery recovered clock and the retransmission process, removing harmful jitter components while preserving the essential clock timing information, thus improving reliability without completely breaking the clock relationship.
2Reliability
If a single clock path is used for retransmission, then the device complexity is low, but the jitter transfer function gain peaks undesirably impair system performance
Solution Approach 1:
The patent implements a dynamic clock path selection mechanism that can switch between the primary recovered clock path and the secondary reference clock path based on jitter conditions. This dynamic approach allows the system to adapt to varying jitter levels, using the simpler single-path structure when conditions are good and the dual-path structure when jitter becomes problematic, thus balancing reliability and complexity.
Solution Approach 2:
The reference clock is designed to serve multiple functions: it acts as a backup clock source when the recovered clock exhibits excessive jitter, and it also serves as a reference for the jitter filter processing. This multi-functionality reduces the need for completely separate systems, thereby limiting the increase in device complexity while still providing the benefits of a dual-path approach.
3Measurement precision
If clock recovery circuit and phase lock loop are used, then clock synchronization is achieved, but process, voltage, and temperature variations cause transfer function peaking that impairs performance
Solution Approach 1:
The patent changes the operational parameters of the phase lock loop by introducing an independent reference clock with stable frequency and phase characteristics. This parameter change allows the system to maintain clock synchronization accuracy while being less sensitive to PVT variations, as the reference clock provides a stable baseline that compensates for environmental variations affecting the recovered clock.
Solution Approach 2:
The patent implements a feedback mechanism where the jitter filter continuously monitors the transmit clock signal quality and adjusts its filtering characteristics accordingly. This feedback loop allows the system to maintain optimal performance by adapting to PVT variations in real-time, preserving both synchronization precision and overall reliability despite environmental changes.
Data Source
AI summary
Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.