Dual-Path RF Receiver Switching for Blocker Rejection and Low Power
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Solution Overview
Problem
Existing RF receivers require substantial power to operate due to the continuous use of phase locked loops (PLLs) to remove blocker signals, which are not effectively addressed in short-distance communication scenarios where blockers are infrequent but can still disrupt communication.
Innovation Solution
A power-efficient receiver architecture that adapts between a low-power state using a diode detector and a higher-power state with a PLL, based on the presence of blocker signals, to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL is continuously used to remove blocker signals, then the ability to reject out-of-band blockers is improved, but power consumption increases substantially
Solution Approach 1:
The receiver dynamically switches between two operational modes: a low-power mode using a diode detector when no blockers are present, and a high-performance mode using a PLL when blockers are detected. This dynamic adaptation allows the system to optimize power consumption while maintaining blocker rejection capability when needed.
Solution Approach 2:
The system changes its operational parameters by switching between different receiver architectures based on blocker presence. The diode detector provides sufficient performance for normal operation, while the PLL is activated only when blocker rejection is required, changing the system's functional parameters adaptively.
2Use of energy by moving object
If a diode detector is used for low-power operation, then power consumption is reduced, but the ability to handle blocker signals is insufficient
Solution Approach 1:
The receiver dynamically switches between two operational modes: a low-power mode using a diode detector when no blockers are present, and a high-performance mode using a PLL when blockers are detected. This dynamic adaptation allows the system to optimize power consumption while maintaining blocker rejection capability when needed.
Solution Approach 2:
A blocker detection mechanism acts as an intermediary that monitors the received signal and triggers the switch from diode detector mode to PLL mode when blockers are detected. This intermediary component enables the system to transition between power states based on actual signal conditions.
3Reliability
If a PLL-based downconverter is used, then out-of-band blockers can be rejected, but device complexity increases
Solution Approach 1:
The receiver is segmented into two distinct processing paths: a simple diode detector path for normal operation and a PLL-based downconversion path for blocker rejection. By segmenting the receiver architecture, the system can activate only the necessary path based on blocker presence, reducing overall complexity compared to always having the PLL path active.
Solution Approach 2:
The system changes its operational parameters by switching between different receiver architectures based on blocker presence. The diode detector provides sufficient performance for normal operation, while the PLL is activated only when blocker rejection is required, changing the system's functional parameters adaptively.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The architecture significantly reduces power consumption by utilizing a low-power path for most operations and switching to a higher-power path only when blockers are detected, maintaining effective communication while optimizing power usage.
Implementation Method 1
a first receiver branch comprising a diode detector configured to receive the input analog signal
Implementation Method 2
a mixer configured to mix the input analog signal with a local oscillator signal
Implementation Method 3
followed by a low pass filter
Implementation Method 4
an analog-to-digital converter configured to produce a first digital signal
Data Source
AI summary
Power efficient receiver architectures are described. A receiver includes a first receiver path having a low power consumption compared to a second receiver path with a higher power consumption but a better ability to remove blocking signals. A multiplexer at the output of both receiver paths is used to select the digital bit stream from either the first path or the second path based on whichever path is currently enabled. The first receiver path can be enabled by default until a blocker signal is detected or the received data is invalid. At such an instance, the first receiver path is disabled and the second receiver path is enabled to remove the blocker and read out the data. The second receiver path may then continue to be enabled for a particular number of pings before switching the output back to the first receiver path.