Dual-Path Sampling Circuit for Short Valid Signal Periods
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Solution Overview
Problem
The increasing operation speed of semiconductor devices makes it difficult to secure reliable sampling operations due to the decreasing period where digital signals maintain a valid and constant logic level, especially under varying process, voltage, and temperature (PVT) conditions.
Innovation Solution
A sampling circuit is designed with multiple sampling units and a delay unit that extends the hold time of digital signals by delaying the data signal for a predetermined time, allowing for a longer valid period and improved reliability of sampling operations, even at higher frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operation speed of semiconductor devices is increased, then productivity is improved, but the period where digital signals maintain valid logic level decreases making sampling operation unreliable
Solution Approach 1:
The patent applies preliminary action by extending the hold time of the data signal before the sampling clock edge. A delay circuit delays the data signal by a predetermined time period, ensuring that the data remains valid for a longer duration before being sampled. This preliminary extension of the valid period allows reliable sampling even at higher operating speeds where the natural valid period would be too short.
2Productivity
If the frequency of digital signal is increased to match higher operation speeds, then productivity is improved, but the period where digital signal maintains valid level continuously decreases making correct operation difficult
Solution Approach 1:
The delay circuit performs preliminary action by extending the hold time of the data signal before the sampling instant. This ensures that even as the valid signal period continuously decreases with increasing frequency, there is always a sufficient margin of valid time available for reliable sampling operation.
Data Source
AI summary
A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.