Dual-Path Timing Wander Removal for Packet Jitter Filtering
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Solution Overview
Problem
Existing systems face challenges in effectively managing large jitter caused by packet delay variations and systematic jitter in timing signals, particularly in optical transport networks, due to the unpredictability of gap patterns and the high cost of ultra-stable oscillators required for low bandwidth filtering.
Innovation Solution
A dual-path approach is implemented, where an excursion detector identifies timing differences above a threshold, allowing an arithmetic circuit to adjust the timing difference digitally, and a loop filter controls an oscillator to separate and filter out systematic and thermal jitter, enabling a higher PLL bandwidth and reducing system costs by using less stringent oscillator stability requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If very low bandwidth jitter cleaning devices are used to filter out jitter caused by clock gaps, then jitter performance is improved, but system response latency increases and cost increases
Solution Approach 1:
The patent segments the jitter cleaning function into two distinct paths: a digital path that handles large systematic jitter from gap insertions, and an analog PLL path that handles random thermal jitter. This segmentation allows each path to be optimized independently, enabling the digital path to provide rapid response without latency while the analog path ensures jitter performance, thereby resolving the contradiction between jitter performance and response latency.
2Reliability
If very low bandwidth jitter cleaning devices are used to filter out jitter caused by clock gaps, then jitter performance is improved, but system cost increases
Solution Approach 1:
The patent divides the jitter cleaning system into two functional segments: a digital processing segment that handles predictable systematic jitter from gap patterns, and an analog filtering segment that handles random thermal jitter. This segmentation allows the use of less expensive components in the digital path while maintaining overall jitter performance, reducing the need for expensive ultra-stable oscillators and very low bandwidth filters, thereby resolving the contradiction between jitter performance and system cost.
Solution Approach 2:
The patent introduces a digital intermediary component (the digital jitter cleaning path with gap detection and correction logic) that processes the timing signal before it reaches the analog PLL. This intermediary handles the bulk of systematic jitter removal, allowing the analog PLL to operate with higher bandwidth and less stringent component requirements, thereby reducing system cost while maintaining jitter performance.
3Reliability
If a 1 mHz loop bandwidth is used to filter out wander in packet-based timing networks, then wander filtering performance is improved, but the base frequency reference needs to be ultra stable which increases cost
Solution Approach 1:
The patent segments the wander filtering function into digital and analog components. The digital path processes packet delay variation timing differences and applies correction, while the analog PLL with higher loop bandwidth handles residual random jitter. This segmentation eliminates the need for ultra-stable oscillators required by very low bandwidth analog filtering, reducing oscillator stability requirements and system cost while maintaining wander filtering performance.
4Ease of manufacture
If gapped clock technique is used to align input and output data rates, then system partitioning cleanliness is improved, but downstream system jitter increases
Solution Approach 1:
The patent introduces a digital jitter cleaning intermediary between the gapped clock source and the downstream system. This intermediary detects gap patterns, calculates timing differences, and applies corrections to remove systematic jitter before the signal reaches downstream systems. This allows the gapped clock technique to be used for clean system partitioning while the digital intermediary eliminates the harmful jitter effect, resolving the contradiction between partitioning cleanliness and downstream jitter.
Data Source
AI summary
A more cost effective wander jitter filter utilizes an excursion detector that receives a timing difference between a first signal and a second signal and supplies a first adjustment amount if a magnitude of the timing difference is above a predetermined threshold and otherwise supplies a second adjustment amount of zero. A summing circuit adjusts a magnitude of the timing difference by the first or second adjustment amount. A loop filter receives the summing circuit output and controls an oscillator. The excursion detector output (first adjustment value or zero according to the magnitude of the timing difference) is low pass filtered and the low pass filtered is reintroduced into the oscillator output or the feedback loop. The excursion detector output is accumulated and used to adjust a phase of the feedback signal from the oscillator.