Dual PDM Microphone Clocking for Lower Standby Power
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Solution Overview
Problem
Conventional dual PDM microphone systems waste power due to both microphones being clocked even when only one is active, leading to high power consumption in CMOS drivers and unused clock circuits.
Innovation Solution
A three-signal interface is introduced, where each PDM microphone has a separate PDMCLK signal while sharing a single PDMDAT line, allowing independent operation and reducing power consumption by disabling the clock for the inactive microphone.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a shared clock signal is used for both microphones in a dual PDM microphone system, then device complexity is reduced and ease of manufacture is improved, but power consumption increases because both microphones must be clocked even when only one is active
Solution Approach 1:
The patent segments the clock signaling by providing separate PDMCLK signals for each microphone channel instead of sharing a single clock line. This allows independent clocking of each microphone, enabling the inactive microphone to be completely powered down while the active microphone receives clock signals, thereby resolving the power consumption issue without requiring complex shared clock arbitration circuits.
Solution Approach 2:
The patent applies local quality by allowing each microphone channel to have its own clocking characteristics and power state. The inactive microphone can be placed in a low-power state with its clock disabled, while the active microphone maintains full operational clocking, optimizing power consumption at the local channel level without affecting the other channel.
2Reliability
If digital PDM microphones are used instead of analog microphones, then noise performance is improved and adaptability is enhanced, but power consumption increases due to digital switching operations
Solution Approach 1:
The patent implements periodic action by enabling the PDM microphone clock and digital processing only during periods when audio capture is required, and disabling them during inactive periods. This allows the system to maintain the noise performance benefits of digital PDM microphones when needed while minimizing power consumption during periods when only one or no microphones are active.
Data Source
AI summary
A clocking technique for reducing the power of PDM microphones in dual microphone systems is disclosed. A clock for a conventional PDM microphone (PDMCLK) is provided by another source. PDM microphones send serial data (PDMDAT) on the rising (“Right”) or falling (“Left”) edge of the PDMCLK clock, depending on how the microphone is configured. In a dual PDM microphone configuration, the microphones alternate sending data on the rising edges (transitions to logic-1) and falling edges (transitions to logic-0) of PDMCLK. Typically, Complementary Metal-Oxide-Semiconductor (CMOS) logic is used to transmit or drive the clock signal to the microphones. CMOS drivers consume power primarily when they transition from a logic-0 to a logic-1 or from a logic-1 to a logic-0. Thus, a free-running clock signal will produce the highest CMOS power consumption. In a dual PDM microphone system, it is desirable to operate in a low power mode with a single microphone at times and to operate with the full functionality (and power consumption) of both microphones at other times. In a conventional system, both PDM microphones share both the PDMDAT and PDMCLK signal lines. Thus both microphones must be clocked even if only one is being used. This wastes power in both the PDMCLK output buffer (driving both loads even if one is not being used) as well as in the unused microphone (where all of the clock circuits are active and switching). A novel PDM microphone interface is disclosed that provides a three signal interface comprising a separate PDMCLK signal to each microphone while maintaining a single common PDMDAT line.