Dual-PFD Feedback Divider With Prescaler-Based Delay Control
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Solution Overview
Problem
High PLL output frequencies require complex frequency multiplication and division in frequency synthesizers, leading to increased noise and power consumption, particularly in maintaining channel spacing and resolution with existing dual-PFD systems.
Innovation Solution
A dual-PFD circuit with delay feedback generated by a dual-modulus prescaler based on mode control from a feedback delay generation circuit, integrating a delay counter into the PLL feedback divider to provide a fixed delay and reduce power consumption by controlling the prescaler mode, thereby improving noise performance and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If complex frequency multiplication and division are used to achieve high PLL output frequencies, then the output frequency range is improved, but noise performance deteriorates and power consumption increases
Solution Approach 1:
The frequency division process is segmented into two stages: a dual-modulus prescaler that divides by M or M+1, and a programmable N counter that divides by N. This segmentation allows the prescaler to handle the bulk of frequency reduction with simple, low-noise logic, while the N counter provides fine-grained control for channel spacing, thereby reducing overall noise compared to a single complex divider.
Solution Approach 2:
The prescaler modulus is made dynamic through mode control signals that switch between M and M+1 division ratios. This dynamic switching enables the system to achieve different effective division ratios (N, N+1, N+2, N+3) by combining prescaler and N counter operations, providing frequency agility without requiring multiple static divider circuits, thus reducing power consumption.
2Speed
If complex frequency multiplication and division are used to achieve high PLL output frequencies, then the output frequency range is improved, but power consumption increases
Solution Approach 1:
The divider is segmented into a prescaler and an N counter, allowing the prescaler to perform the majority of frequency reduction using simple, low-power logic. The N counter handles only the remaining division with higher precision. This segmentation reduces the overall complexity and power consumption compared to using a single programmable counter for the entire division ratio.
Solution Approach 2:
The dual-PFD architecture uses periodic switching between two PFDs with alternating enable signals, allowing one PFD to be active while the other is reset or inactive. This periodic operation reduces average power consumption compared to continuously operating a single PFD with complex feedback, while maintaining the required frequency synthesis functionality.
3Object-generated harmful factors
If a dual-PFD is used to linearize the charge pump transfer function and improve noise performance, then in-band noise performance is improved, but device complexity increases
Solution Approach 1:
The dual-PFD architecture merges the functions of phase detection, frequency detection, and feedback division into an integrated structure where two PFDs share common elements (charge pump, loop filter, VCO) while having separate feedback paths. This merging achieves linearized charge pump transfer function and improved noise performance without requiring completely separate dual feedback loops, thereby controlling complexity.
Solution Approach 2:
The dual-modulus prescaler serves multiple functions: it provides the primary frequency division, generates mode control signals for the N counter, and enables dynamic switching between different division ratios. This multi-functionality reduces the need for separate control circuits and simplifies the overall architecture compared to using multiple independent dividers, thereby reducing complexity while achieving the desired noise performance.
4Measurement precision
If a programmable counter is used for frequency division to maintain channel spacing, then frequency resolution is improved, but device complexity increases
Solution Approach 1:
The frequency division function is segmented between the prescaler (handling coarse division with simple M/M+1 logic) and the N counter (handling fine division for channel spacing). This segmentation allows the N counter to be optimized for precision with a manageable counting range, while the prescaler handles the bulk of frequency reduction with minimal complexity, achieving high resolution without excessive overall complexity.
Data Source
AI summary
A dual-PFD circuit with delay feedback generated by a dual-modulus prescaler based on mode control from a feedback delay generation circuit. The PFD circuit can be used with a PLL feedback divider to divide a VCO clock signal VCO_clk and generate FB and FB_DLY signals. The PLL feedback divider includes a dual modulus prescaler to selectively divide the VCO_clk by either M or M+1 (such as 4/5) based on a divide mode control input to generate a prescaled divide signal, and a programmed counter/divider (N counter/1/N divider) to selectively divide the prescaled divide signal to generate the FB signal, and a delay generation circuit to selectively delay the FB signal by a pre-defined delay to generate the FB_DLY signal. The prescaler is responsive to the pre-defined delay from the delay generation circuit to change divide modes. The dual PFD circuit response to the FB and FB_DLY signals in relation to a reference signal to generate a phase comparison signal. the dual-PFD circuit can be used with a charge-pump coupled to the dual PFD circuit, and responsive the phase comparison signal to generate a frequency tuning voltage, for input to a VCO for generating the VCO clock signal. The dual PFD circuit, charge pump and VCO can be used in a PLL frequency synthesizer.