Dual Phase Accumulator PLL for Fine Frequency Resolution
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Solution Overview
Problem
Existing frequency synthesis devices, such as integer division PLLs, face challenges in optimizing the time to establish the operating regime and the resolution of the multiplicative factor, as well as phase noise and noise resolution, due to limitations in bandwidth and noise amplification from fractional step methods.
Innovation Solution
A frequency synthesis device with a feedback loop incorporating a first and second phase accumulator, where the servo circuit and feedback loop supply distinct logic signals based on continuous phase accumulation values, allowing for implicit modulo operation and eliminating the need for synchronization, thereby increasing resolution without compromising on noise or setup time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If integer division PLL is used, then the device complexity is reduced, but the frequency resolution and adjustment fineness deteriorate
Solution Approach 1:
The invention segments the frequency division function into two independent phase accumulators: one in the reference path and one in the feedback path. This allows the system to achieve fine frequency resolution through the interaction of two simple digital counters rather than requiring a complex fractional divider, thereby maintaining low device complexity while improving frequency resolution.
Solution Approach 2:
The invention replaces the traditional mechanical-like integer division approach with a digital phase accumulation and comparison mechanism. By using digital phase accumulators that count clock cycles and comparing their outputs through logic gates, the system achieves continuous frequency adjustment capability without the limitations of integer division, improving frequency resolution while keeping the digital implementation simple.
2Measurement precision
If fractional step method is used to increase resolution, then the frequency resolution is improved, but phase noise and jitter increase due to noise amplification
Solution Approach 1:
The invention extracts the fractional division functionality from a single complex fractional divider and distributes it across two independent integer phase accumulators. By comparing the outputs of these accumulators directly through logic gates, the system achieves fractional frequency resolution without using a fractional divider, thereby avoiding the noise amplification problem while maintaining high frequency resolution.
Solution Approach 2:
Instead of using a fractional divider to achieve fine frequency resolution (which amplifies noise), the invention inverts the approach by using two integer accumulators whose outputs are compared. This inversion allows the system to achieve the same resolution benefit without the harmful noise amplification effect, as the comparison is performed on clean digital signals from the accumulators.
3Loss of time
If bandwidth is increased to reduce setup time, then the establishment time is reduced, but phase noise and jitter increase
Solution Approach 1:
The invention implements a feedback mechanism where the output of the second phase accumulator (fed back from the VCO path) is continuously compared with the output of the first phase accumulator (from the reference path). This feedback loop allows the system to quickly acquire lock by comparing phase differences directly, reducing setup time while the loop filter maintains low phase noise by properly shaping the feedback signal.
Solution Approach 2:
The invention replaces the traditional analog phase detector and charge pump mechanism with a digital phase comparison approach using logic gates. This substitution allows for faster response and reduced setup time while maintaining low phase noise, as the digital comparison is instantaneous and does not introduce the same noise amplification issues as analog fractional dividers.
4Measurement precision
If synchronization mechanism is added to coordinate phase accumulators, then the measurement precision is improved, but device complexity increases
Solution Approach 1:
The invention merges the phase accumulation and phase comparison functions into a unified digital logic structure. The outputs of the two phase accumulators are directly fed into comparison logic gates, eliminating the need for separate synchronization mechanisms. This integration achieves accurate phase comparison while keeping the device complexity low by using simple digital logic rather than additional control circuits.
Solution Approach 2:
The phase accumulators are designed to automatically wrap around at their maximum count values, providing self-synchronization without external control. This self-service mechanism ensures that the accumulators remain coordinated through their natural operation, eliminating the need for additional synchronization logic and reducing device complexity while maintaining phase comparison accuracy.
Data Source
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AI summary
This frequency synthesis device (100) includes a control circuit (102) for regulating an output frequency (Fc) to a reference input frequency (Fref). This circuit comprises a first phase accumulator (106) clocked at the reference frequency (Fref), a phase comparison block (110), a loop filter (118), and an oscillator (120). It further includes a feedback loop (104) connecting the output to the comparison block (110), which includes a second phase accumulator (122) clocked at the output frequency (Fc).The comparator block (110) includes T phase comparators (112) with logic gates receiving respectively T first logic signals from the servo circuit (102) on T first inputs and T second logic signals from the feedback loop (104) on T second inputs, these T first and second signals having logic levels that depend continuously on the values supplied by the first and second accumulators (106, 122) according to at least one multi-phase matching matrix.