Clock Duty Cycle Correction with Dual Phase Detectors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional duty cycle correction systems for clock signals in memory devices are slow to achieve a locked condition and fail to accurately align the rising and falling edges of clock signals, leading to deviations from a 50% duty cycle, especially during high-speed data transfers.
Innovation Solution
A duty cycle correction system that includes a duty cycle adjustor and phase detectors to align the transitions of clock signals, using a variable delay line and an inverter to adjust the duty cycle, ensuring the clock signal has a 50% duty cycle by comparing and aligning the edges of the clock signal and its inverted version.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional delay locked loop is used to generate clock signals for latching data on both rising and falling edges, then data latching capability is provided, but the duty cycle deviates from 50% and locking speed is slow
Solution Approach 1:
The patent employs two phase detectors that continuously monitor the phase difference between the clock signal and its inverted version, generating feedback signals that drive two separate delay lines. This dual feedback mechanism enables real-time correction of duty cycle deviations, ensuring the clock signal maintains approximately 50% duty cycle while supporting data latching on both rising and falling edges.
Solution Approach 2:
The patent divides the duty cycle correction function into two independent parallel paths: one path corrects the rising edge timing using a first delay line and first phase detector, while the other path corrects the falling edge timing using a second delay line and second phase detector. This segmentation allows each path to independently optimize its edge alignment without interfering with the other, achieving precise 50% duty cycle control.
2Productivity
If the clock signal duty cycle deviates from 50%, then the system can operate, but data latching reliability deteriorates during high-speed transfers
Solution Approach 1:
The dual phase detector configuration provides continuous feedback on both rising and falling edge phase differences. This feedback enables the system to dynamically adjust the delay lines to maintain optimal edge alignment even during high-speed data transfers, preventing data latching errors that would otherwise occur with duty cycle deviations.
Solution Approach 2:
The patent uses variable delay lines that can dynamically adjust their delay characteristics in real-time based on the feedback from the phase detectors. This dynamic adjustment capability allows the system to adapt to changing operating conditions and maintain precise edge alignment during high-speed data transfers, ensuring reliable data latching.
3Device complexity
If a single phase detector is used in the delay locked loop, then the device complexity is reduced, but the locking time increases undesirably
Solution Approach 1:
The patent segments the phase detection function into two parallel detectors, each dedicated to monitoring a specific edge type (rising or falling). This segmentation allows both edges to be monitored and corrected simultaneously rather than sequentially, dramatically reducing the locking time while the modular design keeps the overall system complexity manageable.
Solution Approach 2:
The patent combines two phase detection paths into a unified duty cycle correction system where both phase detectors work together with their respective delay lines to achieve the common goal of 50% duty cycle control. This merging of functions allows parallel operation that speeds up locking while maintaining systematic organization.
Data Source
AI summary
Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.