Dual-Phase Column Counter Layout for Faster CMOS Image Sensor ADCs
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Solution Overview
Problem
Analog-to-digital converters (ADCs) in CMOS image sensors face limitations in speed due to metal IR drop and high power consumption, particularly as image sensor resolution increases, necessitating improved counter performance.
Innovation Solution
The implementation of a hybrid counter with dual phase clock generators and column counters that generate dual phase clock signals, allowing for separate counting of lower and upper bits, which enhances counting speed and reduces power consumption by sharing dual phase clock signals among column counters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a ripple counter is used in ADCs, then the counting function is implemented, but the counting speed is limited to few hundred MHz due to huge peak current and power/ground metal IR drop
Solution Approach 1:
The counter is divided into multiple column counters (e.g., first column counter, second column counter, etc.), each handling a portion of the counting task. Each column counter has its own dual phase clock generator, distributing the clock signal generation load and reducing the peak current demand on a single counter unit, thereby enabling higher counting speeds without excessive power consumption.
Solution Approach 2:
The patent employs dual phase clock signals (first clock signal and second clock signal with different phases) to dynamically control the counting operation. The clock signals are switched between phases to enable continuous counting operation, allowing the counter to maintain high speed operation while managing power consumption through phased clocking rather than continuous full-power operation.
2Measurement precision
If the resolution of image sensor increases, then the measurement precision is improved, but the counter's speed must be higher to satisfy market demands, increasing power consumption
Solution Approach 1:
Multiple column counters are used to handle the increased counting requirements for higher resolution image sensors. Each column counter processes a subset of the total counting tasks, allowing the system to achieve both high resolution (through sufficient counting capacity) and high speed (through parallel processing distribution) without requiring a single counter to operate at excessively high speeds.
Solution Approach 2:
The dual phase clock generator and column counter architecture is designed to be scalable and adaptable to different resolution requirements. The same basic structure can be configured for different resolutions by adjusting the number of column counters and their interconnections, providing a universal solution that maintains optimal speed-performance balance across various image sensor resolutions.
3Productivity
If multiple column counters are used to increase counting capacity, then the productivity is improved, but the device complexity increases
Solution Approach 1:
Multiple column counters are merged under a unified control architecture with shared dual phase clock generators and standardized interconnection patterns. This merging approach increases counting capacity through parallel processing while reducing the complexity that would otherwise result from completely independent counter units, as the shared infrastructure provides economies of scale in the control logic and signal distribution.
Data Source
AI summary
A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters.