Dual Phase Detection Circuit for Stable Delay Locking
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Solution Overview
Problem
Existing phase detection circuits in semiconductor apparatuses face challenges in accurately synchronizing the phase of system clock signals with internal clock signals, leading to issues such as harmonic locking during delay locking operations.
Innovation Solution
A phase detection circuit comprising a clock divider, unit delay, first and second phase detectors, and an initialization signal generator, which generates detection signals by comparing the phases of input and divided clock signals to adjust the delay amount of the output clock signal, and includes an output selector to choose between detection signals based on a locking signal, thereby preventing harmonic locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase detection circuit is used to synchronize clock signals, then phase synchronization accuracy is improved, but harmonic locking occurs during delay locking operations
Solution Approach 1:
The phase detection circuit is divided into two separate phase detectors: a first phase detector for coarse phase detection and a second phase detector for fine phase detection. This segmentation allows each detector to operate in optimized ranges, preventing harmonic locking while maintaining high synchronization accuracy. The first phase detector handles large phase deviations, while the second phase detector refines the synchronization, eliminating the harmonic locking issue that occurs in unified detection circuits.
Solution Approach 2:
An initialization signal generator is introduced as an intermediary component that generates initialization signals based on detection signals from the first phase detector. This intermediary mechanism ensures proper initialization of the delay locked loop before fine phase detection begins, preventing harmonic locking by ensuring the system starts from a known stable state. The initialization signal acts as a mediator between coarse detection and fine detection operations.
2Measurement precision
If the delay amount is adjusted to synchronize clock phases, then phase synchronization is improved, but harmonic locking occurs during the adjustment process
Solution Approach 1:
The delay locking operation is segmented into two distinct stages: coarse delay locking handled by the first phase detector and fine delay locking handled by the second phase detector. Each stage operates with appropriate complexity for its specific function, avoiding the harmonic locking that occurs when a single complex detection mechanism attempts to handle both coarse and fine adjustments simultaneously. This segmentation simplifies each individual operation while achieving high overall precision.
Solution Approach 2:
The system dynamically switches between different phase detection modes based on the locking state. During coarse locking, the first phase detector is active with larger detection ranges. Once coarse locking is achieved, the system transitions to the second phase detector for fine locking with smaller detection ranges. This dynamic adaptation prevents harmonic locking by ensuring the appropriate detection sensitivity is applied at each stage of the delay adjustment process.
3Device complexity
If a single phase detector is used for both coarse and fine detection, then device complexity is reduced, but harmonic locking occurs and measurement precision deteriorates
Solution Approach 1:
Instead of using a single phase detector for both coarse and fine detection, the system segments the detection function into two specialized detectors. The first phase detector is optimized for coarse detection with larger phase ranges, while the second phase detector is optimized for fine detection with smaller phase ranges. This segmentation improves measurement precision for each detection stage while the overall device complexity remains manageable due to the modular architecture and shared components such as the delay line and clock divider.
Data Source
AI summary
A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.