Dual-Response Phase Detector for Low-Power Jitter Control
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits face challenges in achieving both low jitter generation and high jitter tolerance, with separate binary and linear phase detectors either generating high jitter or having poor tolerance, and often suffering from power consumption and mismatch errors.
Innovation Solution
A dual-response phase detector that generates both binary and linear responses using shared sampling circuitry, allowing for the control of a common controllable oscillator to achieve low power consumption and improved jitter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate binary and linear phase detectors are used, then jitter tolerance and jitter generation performance can be optimized respectively, but power consumption increases and mismatch errors occur
Solution Approach 1:
The patent combines binary and linear phase detector functions into a single integrated circuit that generates both binary and linear responses simultaneously. The sampling circuitry is shared between both response types, eliminating the need for separate detector circuits. This merging reduces power consumption by eliminating redundant circuitry while maintaining both jitter tolerance (from binary response) and jitter generation performance (from linear response).
Solution Approach 2:
The phase detector is designed to perform multiple functions: generating binary responses for jitter tolerance, generating linear responses for jitter generation performance, and recovering data from the input data stream. A single circuit implementation provides all these functions through shared sampling circuitry that feeds both binary and linear response generation paths, achieving multi-functionality without requiring separate dedicated circuits for each function.
2Reliability
If separate binary and linear phase detectors are used, then specific jitter performance can be achieved, but component count and mismatch errors increase
Solution Approach 1:
The patent merges binary and linear phase detector circuits into a single integrated structure where sampling circuitry is shared between both response types. This reduces the total component count by eliminating redundant elements while maintaining the distinct binary and linear response generation capabilities needed for optimal jitter performance.
Solution Approach 2:
The unified phase detector circuit performs multiple functions simultaneously: it generates binary responses for jitter tolerance, generates linear responses for jitter generation performance, and recovers data from the input stream. This multi-functional design reduces component count by having a single circuit handle all these tasks rather than requiring separate dedicated circuits for each function.
3Use of energy by moving object
If a single phase detector provides both binary and linear responses, then power consumption and component count are reduced, but achieving both low jitter generation and high jitter tolerance becomes challenging
Solution Approach 1:
Within the unified phase detector, the patent segments the response generation into distinct binary and linear paths that share common sampling circuitry. This segmentation allows each response type to be optimized for its specific jitter performance requirement while sharing the power-consuming sampling infrastructure, thus reducing overall power consumption while maintaining both jitter tolerance and jitter generation performance.
Solution Approach 2:
The patent utilizes parameter changes in the sampling circuitry to generate both binary and linear responses from the same input. By varying the response generation parameters (binary vs. linear processing) while sharing the physical sampling hardware, the circuit achieves both low jitter generation and high jitter tolerance without requiring separate physical circuits, thereby reducing power consumption while maintaining reliability.
Data Source
AI summary
Phase detectors for clock and data recovery circuits are provided herein. In certain implementations, a phase detector includes sampling circuitry that generates a plurality of samples of an input data signal based on timing of a plurality of clock signals, a binary response circuit that processes the plurality of samples to generate a plurality of binary output signals providing a binary detector response, and a linear response circuit that processes the plurality of samples to generate a plurality of linear output signals providing a linear detector response. The phase detector generates one or more data output signals based on the plurality of samples to thereby recover data from the input data signal.