Dual Phase Interpolator Architecture for INL and Jitter Reduction
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Solution Overview
Problem
Conventional phase interpolators suffer from integral nonlinearity (INL) that introduces jitter in recovered clock signals, particularly in high-speed systems with advanced modulation schemes like PAM4, QAM16, and QAM64, leading to degraded performance and reduced noise margin.
Innovation Solution
A variation tolerant linear phase interpolator architecture is implemented using a dual phase interpolator core configuration with a 45-degree code offset, allowing for effective cancellation of INL from 6 least significant bits to 1 LSB and reducing worst-case jitter by over 1 picosecond at 28 GHz, while tolerating PVT variations and frequency changes without additional power or area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional phase interpolator is used, then the device complexity is low, but the manufacturing precision (linearity) deteriorates due to integral nonlinearity introducing jitter
Solution Approach 1:
The phase interpolator is divided into multiple sub-interpolators, each handling a specific phase range. By segmenting the interpolation task across multiple units with different code offsets, the overall linearity is improved while keeping individual sub-unit complexity manageable.
Solution Approach 2:
The patent introduces a code offset dimension to the phase interpolation process. By operating sub-interpolators at different code offsets (e.g., 45-degree offsets), the system transforms a one-dimensional linearity problem into a multi-dimensional solution space where non-linearities can be averaged out.
2Productivity
If advanced modulation schemes (PAM4, QAM16, QAM64) are used to increase data rate, then the productivity increases, but the reliability deteriorates due to reduced timing and noise margin
Solution Approach 1:
The system employs feedback mechanisms where the output of sub-interpolators is combined in a way that compensates for individual non-linearities. This feedback-like correction approach improves the overall timing accuracy without requiring external calibration signals.
Solution Approach 2:
The patent converts the harmful effect of individual sub-interpolator non-linearities into a beneficial averaging effect. By carefully designing the code offsets and combination logic, the individual INL errors cancel each other out, transforming a source of jitter into a mechanism for error reduction.
3Adaptability or versatility
If the phase interpolator operates across wide PVT variations and frequency changes, then the adaptability increases, but the manufacturing precision deteriorates due to increased jitter
Solution Approach 1:
The multi-sub-interpolator architecture is designed to function correctly across a wide range of operating conditions. Each sub-interpolator is designed with universal characteristics that allow them to maintain their relative performance relationships across PVT variations, making the overall system adaptable without sacrificing precision.
Data Source
AI summary
A system includes a sampler, a receiver phase-locked loop circuit configured to provide one or more input clock signals, and a phase interpolation circuit coupled to the receiver phase-locked loop circuit and the sampler. The phase interpolation circuit further includes a first phase interpolator configured to generate a first recovered clock signal based on the one or more input clock signals and a first code, and a second phase interpolator configured to generate a second recovered clock signal based on the one or more input clock signals and a second code, wherein the second code has an interpolation code offset from the first code, wherein the interpolation code offset corresponds to a phase shift in the second recovered clock signal relative to the first recovered clock signal, wherein the outputs of the first phase interpolator and second phase interpolator are configured to be merged.