Dual-Phase Detector PLL for Fast Lock and Fine Frequency Resolution
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Solution Overview
Problem
Phase-locked loops face limitations in achieving fine frequency resolution due to integer division ratio constraints, leading to sidebands in the output signal and reduced loop filter bandwidth, which affects speed and phase noise suppression, and existing DAC compensation methods struggle to accurately compensate for phase errors, especially when the phase-locked loop is not locked.
Innovation Solution
A phase-locked loop design incorporating two control units: one for continuous phase-difference monitoring and another for generating current pulses of predetermined duration to compensate for phase errors, with a selection unit to switch between them, ensuring accurate DAC compensation and improved frequency resolution without adverse effects on loop performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a small reference frequency is used to achieve fine frequency resolution, then frequency resolution is improved, but loop filter bandwidth must be narrowed to remove sidebands, which increases transition time and reduces speed
Solution Approach 1:
The patent divides the frequency control into two independent paths: a coarse control path using a first charge pump and loop filter for fast transitions, and a fine control path using a second charge pump and loop filter for precise frequency adjustment. This segmentation allows each path to be optimized independently, resolving the contradiction between speed and precision.
Solution Approach 2:
The system dynamically switches between coarse and fine control modes based on the operational state. During frequency transitions, the coarse control path is activated for rapid response, while during steady-state operation, the fine control path takes over for precision. This dynamic adaptation resolves the speed-precision tradeoff.
2Object-generated harmful factors
If a narrow loop filter bandwidth is used to remove sidebands, then sideband suppression is improved, but transition time increases and phase noise suppression is reduced
Solution Approach 1:
The patent implements separate loop filters for coarse and fine control paths. The coarse loop filter can have a wider bandwidth enabling fast transitions, while the fine loop filter has a narrower bandwidth for effective sideband suppression. This segmentation allows both contradictory requirements to be satisfied in their respective control paths.
3Device complexity
If integer division ratio is used, then circuit simplicity is maintained, but frequency resolution is limited to reference frequency steps
Solution Approach 1:
The frequency synthesis is segmented into coarse tuning (using integer division ratios for simplicity) and fine tuning (using fractional division ratios for precision). The coarse control handles the bulk frequency adjustment with simple integer dividers, while the fine control provides sub-reference-frequency resolution using fractional dividers, thus maintaining overall circuit simplicity while achieving high frequency resolution.
4Measurement precision
If fractional-N divider is used to achieve fine frequency resolution, then frequency resolution is improved, but transient voltage at VCO input increases requiring DAC compensation
Solution Approach 1:
The patent applies fractional-N division only in the fine control path where it is most needed for precision, while the coarse control path uses simple integer division. This segmentation minimizes the occurrence and impact of transient voltages by limiting fractional division to necessary cases, reducing the burden on DAC compensation circuits.
Data Source
AI summary
A phase-locked loop for generating an output signal that has a predetermined frequency relationship with a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a charge pump arranged to generate current pulses for controlling the signal generator, two control units for controlling a duration of the current pulses generated by the charge pump and a selection unit arranged to select either the first control unit or the second control unit to control the charge pump, wherein a first one of the control units is arranged to continuously monitor a phase-difference between the reference signal and a feedback signal formed from the output signal and to, when selected by the selection unit, control the charge pump to output a current pulse having a duration that is dependent on that phase-difference and a second one of the control units is arranged to, when selected by the selection unit, control the charge pump to output a current pulse of predetermined duration that compensates for a phase error in the feedback signal.