Dual Photodiode Image Sensor Noise Reduction
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Solution Overview
Problem
High dynamic range image sensors face challenges in reducing fixed noise and temporal noise during image acquisition, particularly when detecting flashing luminous sources like pulsed light-emitting diodes.
Innovation Solution
The image sensor design incorporates two photodiodes per pixel with distinct integration periods, split into disjoint sub-periods, and a drive circuit that manages transistor operations to reset and readout nodes in a specific sequence, allowing for interleaved sub-periods to enhance noise reduction and improve detection performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high dynamic range image sensor uses two photodiodes per pixel with split integration periods to detect flashing luminous sources, then the detection capability of flashing sources is improved, but fixed noise and temporal noise are generated during acquisition
Solution Approach 1:
The patent divides the integration period into multiple disjoint sub-periods for the second photodiode, allowing separate acquisition of signal portions. This segmentation enables selective combination of measurements to cancel out fixed pattern noise while maintaining detection of flashing sources. The readout process is also segmented into multiple steps (reset signal, first signal, second signal) that are processed differently to eliminate noise.
Solution Approach 2:
The patent changes the temporal parameters of integration by using different integration periods for the first photodiode (continuous) and second photodiode (split into sub-periods). By varying the integration timing and duration, the sensor captures different phases of flashing sources while creating distinct noise patterns that can be mathematically eliminated through differential processing.
2Reliability
If the sensor integrates one photodiode during a continuous period and another during split sub-periods, then response to flashing sources is improved, but device complexity increases
Solution Approach 1:
The patent makes the readout circuitry universal by using the same readout node and transistors to service both photodiodes. The shared readout infrastructure performs multiple functions: reading continuous integration from the first photodiode and reading split sub-period integrations from the second photodiode. This multi-functionality reduces the need for separate dedicated circuits for each photodiode type.
Solution Approach 2:
The patent employs periodic resetting of the readout node through controlled transistor switching. The reset transistor is periodically activated to clear accumulated charge from the readout node between measurements, enabling the circuit to handle both continuous and periodic (split sub-period) integration modes. This periodic action simplifies the readout mechanism by using timing-controlled switching rather than complex circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly decreases noise during image acquisition, ensuring better detection of flashing sources while maintaining dynamic range performance, particularly under low luminosity conditions.
Implementation Method 1
a first photodiode linked to a capacitive readout node by a first transistor, and a second photodiode linked to a first capacitive storage node by a second transistor
Implementation Method 2
a first photodiode linked to a capacitive readout node by a first transistor, and a second photodiode linked to a first capacitive storage node by a second transistor
Data Source
AI summary
An image sensor includes a plurality of pixels each including a first photodiode linked to a capacitive readout node by a first transistor, and a second photodiode linked to a first capacitive storage node by a second transistor, the first capacitive node being linked to the readout node by a third transistor, and the readout node being linked to a node for applying a reset potential by a fourth transistor.