Dual-Pipeline Memory Fabric Arbitration
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Solution Overview
Problem
Current computer systems with shared memory resources face issues of unfair access allocation and power state management, leading to inefficiencies and potential starvation of devices due to fixed priority arbitration and lack of consideration for power states in memory access.
Innovation Solution
A shared memory fabric with a tightly coupled, dual-pipeline architecture that uses a weighted, age-based arbitration method and QoS functionality to dynamically allocate memory bandwidth based on request deadlines and power states, ensuring predictable and efficient access while preventing starvation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If fixed priority arbitration is used to allocate memory access, then access speed is improved for high priority devices, but fairness deteriorates leading to starvation of lower priority devices
Solution Approach 1:
The arbitration system dynamically adjusts priority based on device age and power state rather than using static fixed priorities. The age-based mechanism continuously updates device priority based on how long they have been waiting, while power state awareness dynamically modifies arbitration decisions based on current power conditions, resolving the contradiction between speed and fairness
Solution Approach 2:
The system changes the arbitration parameters by incorporating device age and power state as variable factors. Instead of fixed priority values, the arbitration algorithm uses dynamic parameters that change based on system state, allowing high priority access when needed while ensuring fairness through age-based adjustments
2Reliability
If round robin arbitration is used to allocate memory access, then fairness is improved, but access speed deteriorates due to equal allocation regardless of need
Solution Approach 1:
The system transforms the equal-time round robin approach by changing the allocation parameter from fixed time slots to dynamic allocations based on device age and power state. This allows the system to maintain fairness through systematic allocation while improving speed by prioritizing devices that have waited longer or are in active power states
3Speed
If memory access is granted without considering power state, then responsiveness is improved, but power consumption increases due to unnecessary state transitions
Solution Approach 1:
The arbitration system incorporates feedback from power state sensors to make informed decisions. By continuously monitoring device power states and using this information in the arbitration logic, the system can determine whether immediate access is necessary or if the device can wait for a more energy-efficient opportunity, thus reducing unnecessary power state transitions
Solution Approach 2:
The system changes the arbitration parameter set to include power state as a critical factor. This allows the arbitration decision to adapt based on power conditions, balancing responsiveness with power efficiency by adjusting access timing based on whether devices are in low-power or active states
4Loss of energy
If aggressive power saving is implemented by keeping memory in low power state, then power consumption is reduced, but access latency increases when memory must exit low power state
Solution Approach 1:
The system performs preliminary actions by keeping memory in active state when arbitration predicts imminent access needs based on device age and activity patterns. This proactive approach prevents the need for urgent power state transitions, reducing access latency while maintaining power efficiency through selective use of low-power states
Data Source
AI summary
Selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system are divided into two independent pipelines. Each pipeline operates independently of the other pipeline, and each accesses only one-half of the system memory, such as even or odd addresses in an interleaved memory. However, the two pipelines are tightly coupled to maintain coherency of the fabric. Coupling may be accomplished, for example, by a shared clock that is one-half of the base clock cycle for the fabric. Each incoming address may be processed by a deterministic hash, assigned to one of the pipelines, processed through memory, and then passed to a credit return.