Dual-Plane Flash Memory Random Program Operation
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Solution Overview
Problem
The existing dual-plane type flash memory devices are limited in operational performance due to their inability to simultaneously program memory blocks with different block addresses, as they can only select and program memory blocks with the same block address, leading to sequential and not simultaneous data operations across planes.
Innovation Solution
The implementation of a dual-plane type flash memory device with separate X-decoders for each plane, allowing the activation and programming of memory blocks with different block addresses, enabling simultaneous programming across both planes during a program operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single X-decoder is used to select memory blocks across multiple planes, then the device structure is simpler, but only memory blocks with the same block address can be selected simultaneously, limiting operational performance
Solution Approach 1:
The patent divides the single X-decoder into multiple independent X-decoders, with each decoder responsible for selecting memory blocks in a specific plane. This segmentation allows simultaneous selection of memory blocks with different block addresses across different planes, thereby improving operational performance while maintaining manageable structural complexity through modular design
2Productivity
If page buffer units share the data I/O circuit, then the device structure is simpler, but data input or output operations cannot be executed simultaneously, reducing productivity
Solution Approach 1:
The patent assigns separate data I/O circuits to each plane, eliminating the sharing constraint between page buffer units. This allows simultaneous data input and output operations across different planes, significantly improving data operation efficiency. The increased structural complexity is justified by the substantial productivity gain enabled by parallel data operations
Data Source
AI summary
A dual-plane type flash memory device having a random program function and program operation method thereof. The flash memory device includes a first plane, a second plane, a first X-decoder, and a second X-decoder. The first plane includes first memory blocks sequentially arranged in a row direction. The second plane includes second memory blocks sequentially arranged in a row direction. The first X-decoder activates one of the first memory blocks in response to a first block address signal. The second X-decoder activates one of the second memory blocks in response to a second block address signal. The block activated by the first X-decoder of the first memory block is different from the block activated by the second X-decoder of the second memory blocks. Accordingly, during a program operation, memory blocks of two planes having different block addresses can be selected and programmed. Accordingly, the operational performance of the flash memory device can be enhanced.