Dual-Plane Memory Array Decoder Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory technologies, such as flash memory, are reaching their scaling limits, necessitating new memory technologies that can meet future storage capacity and access speed demands, with memristive devices offering a promising solution but requiring an efficient addressing scheme to minimize the number of decoders in multi-dimensional arrays.
Innovation Solution
A dual-plane memory array structure is proposed, utilizing a unique conductor structure with intersecting wire segments to reduce the number of decoders needed for accessing individual memory cells, allowing for efficient addressing of memristive devices and other memory technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a multi-dimensional memory array is used to increase storage capacity, then the storage capacity is improved, but the number of decoders required increases
Solution Approach 1:
The patent transitions from a conventional two-dimensional crossbar array to a three-dimensional dual-plane array by stacking multiple memory planes vertically. This dimensional expansion allows memory cells to be addressed through a combination of plane selection and in-plane row/column addressing, effectively increasing storage capacity while distributing the addressing burden across multiple dimensions rather than requiring exponentially more decoders in a single plane.
Solution Approach 2:
The memory array is segmented into multiple independent planes stacked vertically, with each plane containing a subset of the total memory cells. This segmentation allows the addressing system to first select a specific plane (reducing the addressing space) and then address rows and columns within that plane, thereby managing the complexity of decoder circuits by dividing the overall addressing task into hierarchical stages rather than requiring a single complex decoder for the entire array.
2Ease of operation
If more decoders are added to access individual memory cells, then the addressing capability is improved, but the performance degradation and complexity increase
Solution Approach 1:
The addressing capability is enhanced by segmenting the memory space into multiple planes, with each plane having its own simplified row and column decoders. This segmentation allows individual memory cells to be uniquely addressed through a hierarchical addressing scheme (plane selection followed by in-plane row/column selection) while keeping each decoder's complexity manageable, as each decoder only needs to handle a subset of the total addressing space rather than the entire array.
Solution Approach 2:
By adding the plane dimension to the conventional two-dimensional crossbar, the patent creates a three-dimensional addressing space that improves addressing capability without proportionally increasing decoder complexity. The plane selection can be implemented through separate control lines or a simplified decoder stage, while the in-plane row and column decoders maintain their standard two-dimensional functionality, thus enhancing overall addressing capability while distributing complexity across multiple addressing dimensions.
Data Source
AI summary
A memory array has a plurality of conductor structures. Each conductor structure has a top wire segment extending in a first direction, a middle wire segment extending in a second direction at an angle from the first direction, a bottom wire segment extending in a direction opposite to the first direction, and a via connecting the top, middle, and bottom wire segments. A plurality of memory cells in an upper plane of the memory array are formed at intersections of the middle wire segment of each conductor structure with the top wire segments of neighboring conductor structures, and a plurality of memory cells in a lower plane are formed at intersections of the middle wire segment of each conductor structure with the bottom wire segments of neighboring conductor structures.