Dual-Plane Memory Architecture for Data Bus Inversion Storage
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Solution Overview
Problem
Existing memory architectures face challenges in efficiently transmitting and storing Data Bus Inversion (DBI) data, requiring additional storage space and memory elements, which increases manufacturing costs.
Innovation Solution
The proposed solution involves a memory system with two memory planes and a shared data bus, where the first memory plane stores the actual data and the second memory plane stores a single bit of data indicating whether the first data has been inverted, thereby eliminating the need for additional storage space and memory elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional storage space and memory elements are provided to store DBI data, then the memory can transmit and store DBI data, but the manufacturing cost increases
Solution Approach 1:
The existing memory plane is designed to serve dual purposes: storing both regular data and DBI data. The memory plane controller intelligently manages the data bus to multiplex different data types through the same physical storage resources, allowing the memory structure to perform multiple functions without requiring dedicated additional storage elements for DBI data.
Solution Approach 2:
The patent combines the storage of regular data and DBI data into a single memory plane structure. By merging the storage resources and using a unified data bus for both data types, the system eliminates the need for separate storage elements, thereby reducing manufacturing complexity and cost while maintaining full DBI functionality.
2Adaptability or versatility
If additional storage space is provided for DBI data, then DBI data can be stored, but the device complexity increases
Solution Approach 1:
The memory plane controller is designed with multi-functional capabilities to handle both regular data and DBI data through the same storage plane. The controller includes logic to identify, separate, and manage different data types on the data bus, enabling a single memory structure to perform multiple storage functions without requiring additional dedicated storage elements.
Solution Approach 2:
The memory plane controller acts as an intermediary between the data bus and the memory plane, intelligently managing the flow of both regular data and DBI data. This mediator component coordinates the storage operations, ensuring that DBI data and regular data are properly routed and stored without increasing the fundamental memory structure complexity.
3Ease of manufacture
If existing memory architecture is used without modifications, then manufacturing cost is reduced, but DBI data transmission is incompatible
Solution Approach 1:
The memory plane controller incorporates dynamic control logic that can adaptively manage data transmission based on the type of data being transmitted. The controller dynamically routes and manages both regular data and DBI data through the same physical bus and storage plane, enabling the existing memory architecture to become compatible with DBI transmission without structural modifications.
Solution Approach 2:
The system changes the operational parameters of the existing memory architecture by modifying how data is routed and managed at the controller level. By changing the data management parameters and control logic rather than the physical structure, the system enables DBI compatibility while maintaining the original memory design and avoiding increased manufacturing costs.
Data Source
AI summary
A memory device includes a memory array including a first memory plane and a second memory plane, and a peripheral circuit coupled to the memory array and configured to perform an operation. The operation includes receiving a first instruction and input data, and in response to the first instruction, writing first data of the input data to the first memory plane and second data of the input data to the second memory plane. The second data is configured to indicate whether the first data has been performed with an inversion operation prior to transmission.