Dual Plane Interleaved NAND Flash Memory Architecture for Low Read Latency
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Solution Overview
Problem
NAND flash memory devices exhibit lengthy read latency times, limiting their usefulness in applications requiring random data access and short sequential page reads, due to substantial word line and bit line resistive-capacitive delays and small cell current.
Innovation Solution
A dual plane interleaved NAND flash memory architecture with smaller NAND strings and counter-biasing mechanisms is employed to reduce read latency, allowing for gapless reads across page and block boundaries while maintaining high memory density and low power operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional NAND flash memory architecture is used, then high memory density is achieved, but read latency becomes lengthy
Solution Approach 1:
The bit lines are divided into multiple local bit line groups, each associated with a separate global bit line. This segmentation allows parallel read operations across different bit line groups, reducing the overall read latency while maintaining the high density NAND flash architecture.
2Speed
If smaller NAND strings are used to reduce read latency, then read speed improves, but device complexity increases
Solution Approach 1:
The patent introduces a new dimensional organization by creating multiple local bit line groups that can be independently selected and connected to different global bit lines. This multi-dimensional bit line structure enables parallel access paths without requiring fundamental changes to the NAND string architecture itself.
3Productivity
If multiple bit lines are actively coupled during read operations, then read throughput increases, but power consumption increases
Solution Approach 1:
The architecture dynamically connects only the specific local bit line groups that contain the desired data to the global bit lines, while other local bit line groups remain disconnected. This dynamic, on-demand connection approach enables high throughput for the required data while minimizing power consumption by keeping unnecessary bit lines in a high-impedance state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces read latency, making random access and initial page read speeds comparable to NOR flash memory, while preserving the density and power efficiency of NAND flash memory.
Implementation Method 1
The third bias and a channel potential established by the first bias are effective to enable tunneling in the flash memory cells
Implementation Method 2
the flash memory cells in the identified strings having the fourth bias capacitively coupled to the channel regions thereof
Data Source
AI summary
A NAND flash memory achieves low read latency and avoidance of inadvertent programming and program disturb so that the random access and initial page read speeds of the NAND flash memory are generally comparable to that of a NOR flash memory, while preserving the higher memory density and lower power operation characteristics of traditional NAND flash memory relative to NOR flash memory. The reduction in latency is achieved by a NAND memory array architecture which employs a small NAND string, a dual plane interleaved memory architecture, a partitioned NAND array, selectively coupled local bit lines per each global bit line, and a counter-biasing mechanism to avoid inadvertent programming and program disturb.