Dual-PLL Clock Generator for Low-Jitter High-Frequency Signals
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Solution Overview
Problem
Conventional PLL circuits are inadequate for generating low jitter, high frequency clock signals from noisy inputs due to the poor close-in phase noise of LC VCOs and the high cost and difficulty in manufacturing high frequency VCXOs or VCSOs.
Innovation Solution
The use of dual integrated PLL circuits with an off-chip frequency-pullable crystal resonator or VCO module and an on-chip VCO, incorporating intra-PLL frequency doubling to reduce in-band phase noise and RMS jitter, while allowing synchronization between input and output clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a narrow-band PLL with external VCXO or VCSO is used to generate low jitter clock signals, then phase noise is reduced, but manufacturing cost and complexity increase due to high frequency VCXO/VCSO difficulty and expense
Solution Approach 1:
The patent replaces expensive high-frequency VCXO/VCSO components with cheaper LC VCOs and crystal oscillators. By using a dual-PLL architecture where the first PLL uses a low-cost crystal oscillator and the second PLL uses an LC VCO, the system achieves low phase noise without requiring prohibitively expensive high-frequency voltage-controlled crystal or surface-acoustic-wave oscillators.
Solution Approach 2:
The patent divides the frequency multiplication function into two separate PLL stages. The first PLL generates an intermediate frequency signal with low phase noise using a crystal oscillator, and the second PLL multiplies this to the final high frequency using an LC VCO. This segmentation allows each stage to be optimized independently, achieving overall low phase noise while using inexpensive components.
2Ease of manufacture
If LC VCO is used in conventional PLL for high frequency generation, then cost is reduced, but close-in phase noise performance deteriorates
Solution Approach 1:
The patent introduces a crystal oscillator and first PLL stage as an intermediary between the input clock and the LC VCO. This intermediate stage provides a low-phase-noise reference signal to the second PLL, which then drives the LC VCO. The intermediary crystal-based stage cleans up the phase noise before the signal reaches the LC VCO, allowing the inexpensive LC VCO to achieve low phase noise performance.
Solution Approach 2:
The frequency generation is segmented into two independent PLL loops. The first PLL uses a crystal oscillator for low phase noise at an intermediate frequency, and the second PLL uses the LC VCO for high frequency multiplication. By separating the functions, the system leverages the low phase noise of crystal oscillators and the cost-effectiveness of LC VCOs simultaneously.
3Manufacturing precision
If narrow PLL loop bandwidth is used to filter input clock noise, then output phase noise is reduced, but LC VCO close-in phase noise becomes dominant and jitter performance deteriorates
Solution Approach 1:
The patent uses two separate PLL loops with different bandwidth characteristics. The first PLL operates with a narrow bandwidth to filter input noise effectively, while the second PLL is designed with appropriate bandwidth to maintain low jitter performance. This segmentation allows each PLL to be optimized for its specific function without compromise.
Solution Approach 2:
The patent creates a clean copy of the reference signal through the first PLL stage before feeding it to the second PLL. This copied, phase-noise-cleaned signal serves as the reference for the LC VCO, ensuring that the VCO's close-in phase noise does not dominate the overall jitter performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively generates clock signals with reduced in-band phase noise and RMS jitter, achieving improved performance for low cost electronic systems by utilizing widely available and inexpensive oscillators and resonant tank circuits.
Implementation Method 1
an off-chip frequency-pullable crystal resonator or voltage-controlled oscillator (VCO) module
Implementation Method 2
first phase detection circuitry coupled to the first and second electrodes and responsive to an input reference signal and the off-chip VCO signal
Implementation Method 3
frequency alteration circuitry coupled to the second electrode and responsive to the off-chip VCO signal by providing an intermediate signal having a second frequency related to the first frequency
Implementation Method 4
phase lock loop (PLL) circuitry coupled to the frequency alteration circuitry and responsive to the intermediate signal by providing a PLL signal having a third frequency related to the second frequency
Data Source
AI summary
A clock signal generator and conditioner in which dual integrated phase-locked loop (PLL) circuits use an off-chip frequency-pullable crystal resonator or voltage-controlled oscillator (VCO) module and an on-chip VCO with intra-PLL frequency doubling to provide a clock signal with reduced in-band phase noise and RMS jitter. As desired, synchronization between the input and output clocks can also be provided.