Dual-PLL Clock Generation for Fast Lock and Low Jitter
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Solution Overview
Problem
Fast phase locked loop (PLL) lock times and reduced clock jitter are essential for quick state transitions and high input/output transfer rates, particularly in multi-core systems with multiple clock domain crossings, where clock latency is a significant issue.
Innovation Solution
A clock generation system comprising a reference clock generator with a low PLL bandwidth for jitter filtering and a local clock generator with a higher PLL bandwidth for fast lock times, utilizing a multiplexer to select suitable reference clocks and a divider to adjust frequencies, achieving both low jitter and rapid lock times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single PLL with low bandwidth is used for jitter filtering, then clock jitter is reduced, but lock time increases and becomes too slow for quick state transitions
Solution Approach 1:
The system divides the clock generation function into two separate PLLs: a first PLL dedicated to jitter filtering with low bandwidth, and a second PLL dedicated to fast locking with high bandwidth. This segmentation allows each PLL to be optimized for its specific function without compromise, resolving the contradiction between jitter reduction and fast lock time.
Solution Approach 2:
A multiplexer is introduced as an intermediary component that selects between the first PLL output and a divided version of the second PLL output. This mediator enables seamless switching between the jitter-filtered clock and the fast-lock clock, allowing the system to achieve both low jitter and fast lock time by using the appropriate source at different times.
2Loss of time
If a single PLL with high bandwidth is used for fast lock times, then lock time is reduced enabling quick state transitions, but clock jitter increases and limits maximum frequencies
Solution Approach 1:
The system separates the fast locking function from the jitter filtering function by assigning the high bandwidth PLL exclusively to fast locking while the low bandwidth PLL handles jitter filtering. This segmentation allows the high bandwidth PLL to achieve fast lock times without being constrained by jitter filtering requirements.
Solution Approach 2:
The multiplexer acts as an intermediary that directs the output from the high bandwidth PLL through a divider circuit to the second input, enabling the system to utilize the fast-locking capability while maintaining the option to switch to the jitter-filtered output when needed.
3Adaptability or versatility
If multiple clock domain crossings are implemented in multi-core systems, then system functionality is enhanced, but clock latency increases and becomes problematic
Solution Approach 1:
The system provides segmented clock sources that can be independently selected for different clock domains. By having separate PLLs for different functions and using a multiplexer, each clock domain can be configured with the appropriate clock source, reducing unnecessary latency from domain crossings while maintaining system versatility.
Data Source
AI summary
Disclosed herein are clock generator systems comprising first and second stage PLLs thereby allowing for both lower PLL bandwidth filtering and higher bandwidth response, in accordance with some embodiments. Other systems may be disclosed and/or described herein.