Coupled Dual PLL Clock Synchronization for Low Phase Noise

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Solution Overview

Problem

Current clock synchronization methods in telecom/datacom networks face challenges in achieving accurate time-of-day synchronization due to packet delay variations and the inability to synchronize with both Primary Reference Clock (PRC) and IEEE 1588 sources simultaneously, leading to instability and high costs from using Temperature Controlled Crystal Oscillators (TCXOs) and Oven Controlled Crystal Oscillators (OCXOs.

Innovation Solution

A double phase-locked loop (PLL) system with a narrowband PLL and a second PLL with a higher bandwidth, allowing synchronization to both a PRC for frequency stability and a standard clock like UTC for time-of-day synchronization, using a regular low-cost crystal oscillator and minimizing the impact of packet delay variations and oscillator stability issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If a narrow loop bandwidth is used to reduce phase noise, then phase noise is reduced, but the system becomes sensitive to temperature changes and oscillator instability

Engineering Contradiction:
Improvephase noiseVSAvoidfrequency stability
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The invention divides the single PLL into two separate PLLs with different functions: the first PLL (narrowband) focuses on reducing phase noise with a narrow loop bandwidth, while the second PLL (wideband) focuses on maintaining frequency stability with a wider loop bandwidth. This segmentation allows each PLL to be optimized for its specific function without compromise.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention merges the outputs of two separate PLLs through a coupler to produce a common output clock signal. The coupler combines the phase-noise-reduced signal from the first PLL with the frequency-stabilized signal from the second PLL, achieving both phase noise reduction and frequency stability simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If TCXO or OCXO is used to maintain frequency stability, then frequency stability is improved, but system cost increases significantly

Engineering Contradiction:
Improvefrequency stabilityVSAvoidsystem cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The invention replaces expensive TCXO or OCXO components with a regular, low-cost crystal oscillator. The frequency stability function is achieved through the second wideband PLL rather than through an expensive temperature-controlled or oven-controlled oscillator, significantly reducing system cost while maintaining performance.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The invention replaces the mechanical/thermal control mechanisms of TCXO (temperature compensation circuits) and OCXO (oven heating elements) with a digital/wideband PLL-based frequency stabilization system. This substitution eliminates the need for complex thermal management hardware while achieving the same frequency stability goal.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If synchronization to both PRC and IEEE 1588 sources is attempted simultaneously, then time-of-day synchronization accuracy is improved, but system complexity and instability increase

Engineering Contradiction:
Improvetime-of-day synchronization accuracyVSAvoidsynchronization system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The synchronization system is segmented into two independent but coupled PLL loops: the first PLL handles phase noise filtering for time-of-day synchronization from IEEE 1588 sources, while the second PLL handles frequency stabilization from PRC sources. This segmentation allows simultaneous synchronization to both sources without direct interference or complexity conflicts.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9444470B2Double phase-locked loop with frequency stabilization
Publication Date: 2016.09.13 MICROSEMI SEMICON
  • US9444470B2 patent drawing
  • US9444470B2 patent drawing
  • US9444470B2 patent drawing

AI summary

A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first and second phase-locked loops to provide a common output. The double phase-locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks.