Dual-PLL Clock Generation for Low Jitter and Wide Tuning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current clock generators in network communication systems are power-inefficient, bulky, and costly, failing to provide clock signals with low phase noise and jitter required for high data rates and higher order modulation.
Innovation Solution
A clock generation circuit with dual phase-locked loops (PLLs) is employed, where one PLL has a higher gain for quick response to frequency drift and the other uses a high-Q, low-noise VCO to generate a low-noise output clock signal, with a switch to control the second PLL's operation and achieve lock at a predetermined control voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If current clock generators are used to provide clock signals, then the system can operate, but the power consumption is high, the device is bulky, and the cost is high while failing to provide low phase noise and jitter
Solution Approach 1:
The clock generation system is divided into two separate PLLs with different functions: first PLL handles frequency synthesis and tuning, while second PLL is dedicated to low-noise clock generation. This segmentation allows each PLL to be optimized for its specific function, improving overall power efficiency and performance.
Solution Approach 2:
The outputs of the first PLL and second PLL are combined through mixing to produce the final clock signal. This merging approach allows the system to leverage the frequency tuning capability of the first PLL and the low-noise characteristics of the second PLL, achieving both power efficiency and low phase noise/jitter.
2Reliability
If a single PLL is used for clock generation, then the device complexity is reduced, but the ability to provide low phase noise and low jitter while maintaining wide tuning range is compromised
Solution Approach 1:
The system uses two PLLs with distinct roles: first PLL for frequency synthesis with wide tuning range, and second PLL for low-noise clock generation. This functional segmentation enables the system to meet both wide tuning range and low phase noise requirements without requiring a single overly complex PLL.
Solution Approach 2:
The first PLL serves multiple purposes: frequency synthesis, providing tuning range, and generating a signal for mixing. The second PLL specializes in low-noise clock generation. This multi-functionality approach allows the system to achieve complex performance goals through coordinated simple components.
3Speed
If higher gain is used in PLL for quick response to frequency drift, then the response speed improves, but the phase noise may increase
Solution Approach 1:
The first PLL is designed with higher gain for quick response to frequency drift and wide tuning range, while the second PLL is optimized for low phase noise with narrower tuning range. By segmenting the functions, the system achieves fast response without compromising phase noise performance in the final clock output.
Solution Approach 2:
Different parts of the system have different quality characteristics: the first PLL has high gain and wide tuning range suited for frequency acquisition and drift correction, while the second PLL has low noise characteristics suited for clean clock generation. Each component's local quality is optimized for its specific function.
4Reliability
If a high-Q, low-noise VCO is used in the second PLL, then the output clock signal has low noise, but the tuning range is limited
Solution Approach 1:
The tuning range function is assigned to the first PLL, while the low-noise clock generation function is assigned to the second PLL with its high-Q VCO. The first PLL's output is mixed with the second PLL's output, allowing the system to achieve both wide tuning range and low noise performance.
Solution Approach 2:
The first PLL acts as an intermediary that provides frequency tuning capability. Its output is mixed with the second PLL's low-noise output, enabling the system to access a wide frequency range while maintaining low phase noise from the second PLL.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a low-noise, low-jitter output clock signal with a wide tuning range, improving power efficiency and reducing costs while meeting the requirements for high data rates and modulation orders.
Implementation Method 1
a first phase-locked loop (PLL) and a second PLL that are coupled in parallel with one another. The first PLL and second PLL may receive a same feedback signal and a same reference signal
Implementation Method 2
The first PLL may include a first voltage-controlled oscillator (VCO) and the second PLL may include a second VCO
Implementation Method 3
The first and second output signals may be combined (e.g., by a frequency mixer) to generate an output clock signal
Data Source
AI summary
Embodiments provide a clock generation circuit with a first phase-locked loop (PLL) and a second PLL that are coupled in parallel with one another and receive a same feedback signal. The first and second PLLs generate respective output signals that are combined to generate an output clock signal. A version of the output clock signal may be passed back to the first and second PLLs as the feedback signal. In some embodiments, the second PLL may include a switch to selectively close the second PLL after the first PLL has locked. In some embodiments, the second PLL may include a bulk acoustic wave (BAW) voltage-controlled oscillator (VCO) and the first PLL may include a different type of VCO.