Dual-PLL Feedforward Divider Control for Wide-Range Low-Jitter Clocks
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Solution Overview
Problem
Analog phase locked loops (PLLs) face challenges in reducing the ring VCO frequency range, particularly as supply voltage scales below 1.2V, while demanding wider frequency ranges from a single PLL, which is not adequately addressed by existing designs.
Innovation Solution
A dual-PLL architecture with dynamically adjustable feedforward divider factors, allowing for a wide frequency range of 500:1, where each sub-PLL has a voltage-controlled oscillator and a feedforward divider circuit, with control circuitry selecting division factors based on output clock signals and voltage inputs to maintain optimal operation across varying PVT conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the supply voltage is scaled below 1.2V to reduce power consumption, then power efficiency is improved, but the VCO frequency range is reduced
Solution Approach 1:
The patent divides the frequency multiplication function into two separate stages: a feedforward divider stage and a feedback divider stage. The feedforward divider (dividing by N) operates before the VCO, while the feedback divider (dividing by M) operates in the traditional PLL feedback path. This segmentation allows the VCO to operate at a lower frequency with reduced voltage requirements, while still achieving high output frequencies through the combined division ratio (N×M), thus resolving the contradiction between low power consumption and wide frequency range.
2Adaptability or versatility
If a single PLL is designed to cover a wide frequency range, then frequency versatility is improved, but jitter performance deteriorates
Solution Approach 1:
The patent implements dynamic switching between different division ratios (N and M) based on the desired output frequency. The control logic dynamically adjusts the feedforward divider ratio N and feedback divider ratio M to optimize performance for different frequency ranges. This dynamic adaptation allows the system to maintain low jitter by selecting appropriate division ratios that keep the VCO operating in its optimal frequency range, while still covering a wide overall frequency range of 500:1.
3Reliability
If conservative margins are used to maintain stability under PVT variations, then reliability is improved, but frequency range is reduced
Solution Approach 1:
The patent changes the operational parameters of the PLL by introducing variable division ratios N and M that can be adjusted based on process, voltage, and temperature (PVT) conditions. The control circuitry monitors PVT variations and dynamically adjusts the division factors to maintain optimal loop bandwidth and stability margins. This parameter adaptation allows the system to maintain reliability under PVT variations without sacrificing frequency range, as the division ratios can be optimized for each operating condition.
Data Source
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AI summary
In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.