Dual-PLL Frequency Synthesizer for Low Phase Noise Spacing
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Solution Overview
Problem
Existing frequency synthesizers face challenges in achieving low phase noise while maintaining narrow channel spacing, as the phase noise increases with reduced channel spacing and bandwidth, limiting their performance in applications requiring dense frequency outputs.
Innovation Solution
A frequency synthesizer design incorporating both integer-N and fractional-N phase locked loops, where the integer-N loop provides a high-frequency signal with a large bandwidth to minimize phase noise degradation, and the fractional-N loop outputs a signal with a reduced frequency to achieve narrow channel spacing, with a frequency adder combining these signals to produce the final output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the reference frequency is reduced to achieve narrow channel spacing, then the channel spacing is reduced, but the bandwidth is reduced and phase noise is increased
Solution Approach 1:
The frequency synthesizer is divided into two independent phase-locked loops: an integer-N PLL and a fractional-N PLL. Each loop operates with different reference frequencies and bandwidths, allowing them to independently optimize for their respective functions. The integer-N PLL uses a high reference frequency (e.g., 10 MHz) with wide bandwidth to minimize phase noise, while the fractional-N PLL uses a low reference frequency (e.g., 100 kHz) with narrow bandwidth to achieve fine channel spacing. Their outputs are combined through frequency addition to produce the final synthesized signal.
2Stability of the object's composition
If the bandwidth of the phase locked loop is reduced to maintain stability with low reference frequency, then the phase locked loop stability is maintained, but the phase noise is increased due to voltage controlled oscillator phase noise
Solution Approach 1:
The system segments the phase-locked loop functionality into two independent loops with different stability and noise characteristics. The integer-N PLL operates with wide bandwidth for low phase noise, while the fractional-N PLL operates with narrow bandwidth for stability at low reference frequency. By separating these functions, each loop can be optimized independently without compromising the other.
3Device complexity
If a single phase locked loop is used to achieve both wide bandwidth for low phase noise and narrow channel spacing, then the system complexity is reduced, but it is impossible to simultaneously achieve low phase noise and narrow channel spacing
Solution Approach 1:
Rather than attempting to design a single PLL that simultaneously achieves conflicting performance targets, the system segments the functionality into two specialized PLLs. This segmentation allows each loop to be independently optimized for its specific function, achieving overall system performance that would be impossible with a single loop.
Solution Approach 2:
The outputs of the two phase-locked loops are combined through frequency addition in a frequency adder circuit. The integer-N PLL output and fractional-N PLL output are summed to produce the final synthesized frequency, merging the advantages of both loops into a single output signal.
Data Source
AI summary
The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency.