Dual-PLL Architecture for Fast Output Frequency Switching
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in quickly switching their output frequency due to their low bandwidth, which is designed to minimize jitter but results in slow frequency changes.
Innovation Solution
Implementing a second PLL with high bandwidth as a controlled oscillator, allowing for rapid frequency changes by adjusting the configuration of both the first and second PLLs, including changing divisors and voltage inputs, to decouple the bandwidth from the first PLL's narrow bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the PLL bandwidth is reduced to minimize jitter, then the output clock jitter is reduced, but the frequency switching speed becomes slow
Solution Approach 1:
The patent segments the frequency control function into two independent PLLs: the first PLL maintains low bandwidth for minimal jitter, while the second PLL provides high bandwidth for fast frequency switching. This segmentation allows each PLL to specialize in one function, resolving the contradiction between jitter reduction and switching speed.
Solution Approach 2:
The second PLL acts as an intermediary between the frequency control input and the first PLL's controlled oscillator. It rapidly adjusts its own oscillator frequency in response to frequency change requests, then feeds this adjusted frequency to the first PLL, which fine-tunes the final output frequency with minimal jitter.
2Speed
If the first PLL bandwidth is increased to improve frequency switching speed, then the frequency switching becomes faster, but the output clock jitter increases
Solution Approach 1:
The patent divides the frequency control functionality into two separate PLL units with different bandwidth characteristics. The first PLL is designed with low bandwidth specifically for jitter minimization, while the second PLL uses high bandwidth for rapid frequency transitions. This functional segmentation eliminates the need to compromise between these conflicting requirements in a single PLL.
Solution Approach 2:
The system dynamically switches between two operational modes by using two PLLs with different characteristics. During frequency transitions, the second high-bandwidth PLL dominates the response, providing fast switching. During steady-state operation, the first low-bandwidth PLL maintains minimal jitter. This dynamic utilization of different PLL characteristics resolves the contradiction.
Data Source
AI summary
A phase-locked loop (PLL) is implemented to have another (second) PLL in place of the controlled oscillator. When a known frequency change in the frequency of the output clock is desired, in addition to changing a configuration of the PLL (first PLL), the configuration of the second PLL is also changed to cause the frequency of the output clock to change quickly. In various embodiments, the configuration of the second PLL is changed by changing the divisor of the feedback divider of the second PLL, the divisor in a pre-scaler in the second PLL, the control voltage of a VCO used in the second PLL, and any other point of user control in the second PLL.