Dual-PLL Clock Synchronization for Fine NFC Phase Alignment
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Solution Overview
Problem
Existing NFC devices with small loop antennas face challenges in achieving high-resolution phase variation between the PCD clock and active load modulated signals without consuming excessive power or chip area, particularly in synchronizing the phase during active load modulation.
Innovation Solution
The apparatus employs a phase adjustment mechanism that adds an offset to the sigma-delta modulator's input or output, utilizing a frequency controlled oscillator and phase detector to vary the fractional divider ratio, allowing for high-resolution phase adjustment without increasing power consumption or chip area, and includes control logic to modulate the antenna loading and adjust phase differences before and after transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a load-modulation switch is used to alter impedance loading of the antenna, then the NFC antenna signal can be modulated, but it is not possible to achieve high-resolution phase variation between PCD clock and load modulated signal
Solution Approach 1:
The patent changes the operating parameters of the phase detector by allowing it to detect phase differences over multiple cycles (e.g., 32 cycles) rather than a single cycle. This enables high-resolution phase measurement by accumulating phase information over time, achieving fine phase control without requiring additional hardware components.
2Power
If active load modulation is implemented to reach ISO required load modulation amplitude, then the NFC communication range is improved, but the phase synchronization between PCD carrier and PICC signal becomes more difficult to maintain
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector continuously monitors the phase difference between the PCD carrier signal and the PICC transmitted signal. The detected phase error is fed back to adjust the timing of the active load modulation, ensuring that the transmitted signal remains synchronized with the carrier despite the high-power modulation requirements.
Solution Approach 2:
The system performs preliminary phase detection and adjustment before the actual active load modulation occurs. By pre-synchronizing the phase relationships and establishing the correct timing offsets in advance, the system ensures that when high-power modulation occurs, the phase synchronization is already optimized, maintaining reliability during power-intensive operation.
3Measurement precision
If high-resolution phase adjustment is implemented using traditional methods, then phase control precision is improved, but power consumption and chip area increase significantly
Solution Approach 1:
The patent makes the existing phase detector and frequency divider circuits perform multiple functions. The phase detector not only detects phase differences for synchronization but also provides high-resolution phase measurement for control. The frequency divider serves both to generate clock signals and to enable multi-cycle phase accumulation. This multi-functionality achieves high-resolution phase control without adding dedicated high-resolution adjustment hardware, thereby avoiding increased power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables precise phase adjustment between the input and output signals, minimizing the need for re-synchronization and reducing power and area consumption, thus enhancing the efficiency of NFC communication.
Implementation Method 1
a first phase locked loop (PLL) circuit and a second PLL circuit. The first PLL circuit receives a stable reference-oscillation signal, and, in response to a PLL-PLL control signal indicating a frequency offset, adjusts a fractional divider ratio of the first PLL circuit
Implementation Method 2
The first phase locked loop may comprise a frequency controlled oscillator, and the frequency divider may comprise a post-divider configured to receive the output of the frequency controlled oscillator and to output the output signal. The frequency controlled oscillator may be a digitally controlled oscillator, or a voltage controlled oscillator.
Data Source
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AI summary
Apparatus for clock synchronisation comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.