Dual-PLL Clock Synchronization for NFC Load Modulation
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Solution Overview
Problem
Wireless communication devices, particularly those using near-field communication (NFC), face challenges in maintaining efficient and reliable data transmission due to issues like signal loss and corruption, especially when devices are not synchronized or when signal quality is inadequate.
Innovation Solution
The implementation of a dual phase-locked loop (PLL) circuit system in a proximity coupling device (PCD) that adjusts a fractional divider ratio in response to frequency offsets, ensuring synchronization and maintaining synchronization during active load modulation by using a stable reference-oscillation signal and a feedback path with a post-divider circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If active load modulation is used to strengthen signal transmission from PICC to PCD, then signal strength is improved, but synchronization between PICC and PCD is lost because the active modulation signal overwrites the PICC
Solution Approach 1:
The system separates synchronization functions into two distinct PLL circuits: a first PLL dedicated to receiving and tracking the carrier signal for synchronization, and a second PLL for generating the modulation signal. This segmentation allows the modulation signal to be strong without interfering with the synchronization function, as each PLL operates independently on its own signal path.
Solution Approach 2:
The first PLL acts as an intermediary between the received carrier signal and the synchronization control mechanism. It processes the carrier signal to extract timing information and generates control signals that regulate the modulation depth, thereby mediating between the need for strong modulation and maintaining synchronization.
2Area of stationary object
If the distance between devices is increased to expand communication range, then coverage area is improved, but data transmission becomes lost or corrupt
Solution Approach 1:
The system employs feedback mechanisms where the first PLL continuously monitors the received carrier signal quality and adjusts the modulation parameters accordingly. This feedback loop ensures that even at increased distances, the modulation depth and timing are optimized to maintain data transmission integrity and prevent corruption.
Solution Approach 2:
The modulation parameters are made dynamic rather than fixed. The system continuously adapts modulation depth, frequency, and timing based on real-time signal conditions detected by the PLL circuits, allowing the communication system to maintain reliability across varying distances and channel conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability and efficiency of NFC communication by maintaining synchronization and frequency stability between a PCD and a proximity integrated circuit card (PICC), reducing signal loss and corruption, and ensuring compliance with international standards.
Implementation Method 1
a first phase locked loop (PLL) circuit configured and arranged to receive a carrier signal that is transmitted over a communications channel from a non-synchronous device
Implementation Method 2
adjust, in response to the PLL-PLL control signal indicating a frequency offset, a fractional number by which the feedback divider circuit or the post-divider circuit operates
Data Source
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AI summary
Various aspects of the present disclosure are directed apparatuses and methods including a first phase locked loop (PLL) circuit and a second PLL circuit. The first PLL circuit receives a carrier signal that is transmitted over a communications channel from a non-synchronous device, and generates a PLL-PLL control signal. The second PLL circuit receives a stable reference-oscillation signal, and, in response to the PLL-PLL control signal indicating a frequency offset, adjusts a fractional divider ratio of the second PLL circuit. The first PLL circuit and the second PLL circuit are configured to produce an output frequency signal that is synchronous to the carrier signal.