Dual-PLL Radar Frequency Ramping Without Fractional N Spurs
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Solution Overview
Problem
Radar MMICs face issues with fractional N spurious outputs in the frequency range of the ramping signal, which can mask small targets and increase noise, preventing their detection due to the generation of unwanted spurious products by the fractional multi-modulus divider (MMD) in phase-locked loop (PLL) circuits.
Innovation Solution
A method involving a first PLL generating a ramping signal based on a first reference signal within a radar frequency band, and a system clock generating a second reference signal with a common system reference frequency, which is used by a second PLL to produce the first reference signal for the first PLL, ensuring that fractional spurs are eliminated from the frequency range by creating an integer-free frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fractional multi-modulus divider (MMD) is used in the PLL circuit to generate a ramping signal, then the frequency resolution and adaptability of the radar system are improved, but fractional N spurious outputs are generated within the radar frequency band, increasing noise and masking small targets
Solution Approach 1:
The patent divides the PLL system into two independent parts: a first PLL that generates the ramping signal for frequency sweeping, and a second PLL that generates the reference signal. This segmentation allows each PLL to operate independently, with the second PLL's reference signal specifically designed to prevent fractional spurs in the first PLL's output, thereby resolving the contradiction between frequency resolution and spurious output generation
Solution Approach 2:
The second PLL acts as an intermediary system that generates a reference signal tailored to eliminate fractional N spurious outputs. By introducing this intermediate reference signal generation stage, the system achieves both high frequency resolution through fractional MMD division and suppression of spurious outputs, as the second PLL's reference frequency is specifically chosen to avoid creating harmful fractional spurs
2Device complexity
If the MMD dividing coefficient is set close to an integer value to simplify the divider operation, then the device complexity is reduced, but a wide set of spurious with high levels is generated, masking radar signals
Solution Approach 1:
The patent changes the reference frequency parameter generated by the second PLL to specifically counteract the spurious outputs. By adjusting the reference frequency based on the MMD dividing coefficient and the desired suppression of fractional spurs, the system maintains simple integer-based division operations while eliminating the harmful spurious signals that would otherwise mask radar targets
3Speed
If the reference frequency Fref is increased to improve the PLL locking speed and reduce settling time, then the response time is improved, but integer spurs occur at higher frequencies within the radar band, reducing measurement precision
Solution Approach 1:
By separating the reference signal generation into an independent second PLL, the system can optimize the reference frequency for fast locking speed without compromising target detection accuracy. The second PLL's reference frequency is specifically designed to avoid integer spur frequencies that would fall within the radar measurement band, thus maintaining both fast response and high precision
Data Source
AI summary
A signal generator includes a first phase-locked loop (PLL) configured to receive a first reference signal having a first reference frequency and generate a ramping signal based on the first reference signal, where the ramping signal is between a minimum frequency and a maximum frequency of a radar frequency band; a system clock configured to generate a second reference signal having a common system reference frequency; and a second PLL configured to receive the second reference signal from the system clock, generate the first reference signal based on the second reference signal, and provide the first reference signal to the first PLL.