Dual-PLL RF Synchronization for Broadband Coherent Communication
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Solution Overview
Problem
Existing RF communication systems face challenges in achieving phase synchronization for broadband coherent communication, particularly due to high RF phase ambiguity and dynamic phase offset, and are limited by noise sensitivity and complex configurations requiring high-power ADCs and I/Q demodulation.
Innovation Solution
A dual-PLL architecture is implemented, utilizing a baseband-driven PLL to provide a reference for an RF PLL, achieving phase synchronization without a forwarded clock, and setting a predetermined relationship between carrier frequency and data rate to mitigate negative-frequency side-lobe effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a forwarded clock is used for phase synchronization in RF communication, then phase synchronization is achieved, but the PLL dividing ratio becomes very large which increases noise sensitivity and RF phase ambiguity
Solution Approach 1:
The patent divides the single PLL system into two separate PLLs: a baseband PLL operating at lower frequency and an RF PLL operating at higher frequency. The baseband PLL generates a reference clock that feeds the RF PLL, eliminating the need for a large dividing ratio in a single PLL and thereby reducing noise sensitivity while maintaining phase synchronization capability.
Solution Approach 2:
The baseband PLL acts as an intermediary between the reference clock source and the RF PLL. It generates an intermediate reference frequency that reduces the dividing ratio required by the RF PLL, thereby reducing noise sensitivity and RF phase ambiguity while still enabling accurate phase synchronization.
2Reliability
If I/Q demodulation is used for phase synchronization, then phase synchronization is achieved, but the system configuration becomes significantly complicated and high-power ADCs are required
Solution Approach 1:
The patent extracts the phase synchronization function from the complex I/Q demodulation system and implements it through a dedicated dual-PLL architecture. This separates the phase locking function from the data demodulation process, achieving accurate phase synchronization without requiring complicated I/Q demodulation circuits or high-power ADCs.
Solution Approach 2:
The dual-PLL system performs phase synchronization autonomously using feedback from the received signal. The baseband PLL locks to the baseband component and the RF PLL locks to the RF carrier, with both PLLs self-adjusting their phases without requiring external I/Q demodulation or complex processing, thereby simplifying the overall system configuration.
3Loss of energy
If a forwarded reference clock is used at very low frequency to reduce transmission loss, then transmission loss is reduced, but the PLL dividing ratio increases which increases RF phase ambiguity
Solution Approach 1:
The patent segments the frequency multiplication function into two stages: the baseband PLL operates at low frequency to minimize transmission loss, and the RF PLL multiplies this frequency to the required RF carrier frequency. This segmentation allows the low-frequency clock to be transmitted with minimal loss while the high-frequency RF PLL generates the carrier with reduced phase ambiguity due to its smaller dividing ratio.
Solution Approach 2:
The baseband PLL serves as an intermediary that generates a low-frequency reference clock which is then fed to the RF PLL. This intermediary approach allows the system to benefit from low transmission loss at baseband frequencies while the RF PLL handles the high-frequency carrier generation with a manageable dividing ratio, thereby reducing RF phase ambiguity.
Data Source
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AI summary
According to one aspect of the present disclosure, there is provided a system for implementing a broadband radio frequency (RF) communication, including: a first phase locked loop (PLL) unit configured to generate a first clock based on a reference clock; and a second PLL unit configured to generate a second clock based on the first clock generated by the first PLL unit and a baseband signal generated by demodulating a reception signal, wherein the second clock is provided to the first PLL unit as the reference clock, and a carrier frequency used for demodulating the reception signal is determined by the first clock.