Dual-PLL Fractional Synthesizer for Integer Boundary Spur Mitigation
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Solution Overview
Problem
Existing PLL circuits face challenges in minimizing die area while generating output clocks with frequencies that are multiples of the input clock, particularly when the multiplication factor is of the form N.F, where N is an integer and F is a fraction, leading to undesired spectral components.
Innovation Solution
The implementation of a clock generation circuit using a pair of PLL circuits with feedback divider circuits, where the first input clock is generated based on the second output clock, allowing for programmable division and multiplication factors to minimize the fraction portion F, thereby reducing or eliminating undesired spectral components and achieving minimal die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single PLL circuit is used to generate output clocks with frequency multiplication factor N.F, then the die area is minimized, but undesired spectral components appear at frequency N times the input clock frequency
Solution Approach 1:
The patent divides the frequency synthesis function into two separate PLL circuits. The first PLL generates an intermediate clock with multiplication factor N1.F1, and the second PLL generates the final output clock with multiplication factor N2.F2. This segmentation allows each PLL to operate with optimized parameters, reducing the fraction portion F in each stage and thereby minimizing undesired spectral components while maintaining compact die area through functional division.
2Object-generated harmful factors
If the fraction portion F of the multiplication factor N.F is minimized, then undesired spectral components are reduced, but the circuit complexity increases
Solution Approach 1:
The patent combines two PLL circuits in a cascaded configuration where the output of the first PLL serves as the input to the second PLL. This merging of functions allows the system to achieve a small effective fraction portion F by distributing the multiplication across two stages, thereby reducing spectral components at frequency N times the input clock while managing circuit complexity through integrated design.
3Object-generated harmful factors
If multiple PLL circuits are used to reduce undesired spectral components, then the spectral purity is improved, but the die area increases
Solution Approach 1:
The patent implements a nested configuration where the first PLL circuit is effectively nested within the overall frequency synthesis system, with its output serving as the input to the second PLL. This nesting allows the two PLL circuits to share common resources such as the crystal oscillator and feedback divider circuits, thereby improving spectral purity through multi-stage frequency multiplication while minimizing the increase in die area through resource sharing.
Data Source
AI summary
A clock generation circuit is disclosed. The clock generation circuit includes a first PLL circuit configured to generate a first output clock based on a first input clock, where the first PLL circuit includes a first feedback divider circuit. The clock generation circuit also includes a second PLL circuit configured to generate a second output clock based on a second input clock, where the second PLL circuit includes a second feedback divider circuit. The first input clock is generated based on the second output clock.