Dual PLL Circuit for Accurate Time-to-Digital Conversion
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Solution Overview
Problem
Existing time-to-digital conversion technologies face challenges in accuracy and complexity due to reliance on edge matching detection, which requires synchronization of clock pulses and is prone to errors, especially when clock frequencies do not coincide, leading to increased conversion time and reduced accuracy.
Innovation Solution
A circuit device employing dual PLL circuits for phase synchronization between two clock signals of different frequencies, allowing for improved phase matching and reduced error, enabling faster and more accurate time-to-digital conversion by generating a reference clock signal and using frequency dividers for feedback control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If edge matching detection is used to synchronize clock pulses, then time-to-digital conversion can be performed, but the conversion time increases and accuracy deteriorates when clock frequencies do not coincide
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the phases of first and second clock signals using PLL circuits before they are used in the time-to-digital conversion circuit. This ensures that the clock signals are already phase-aligned when needed, eliminating the need for real-time edge matching detection during conversion, thus reducing conversion time while maintaining accuracy
Solution Approach 2:
The patent introduces PLL circuits as intermediary devices between the clock signal sources and the time-to-digital conversion circuit. These PLL circuits act as mediators that synchronize the phases of clock signals with different frequencies, enabling accurate time-to-digital conversion without requiring the clock frequencies to naturally coincide, thereby improving accuracy while maintaining efficient conversion timing
2Measurement precision
If edge matching detection is used to detect synchronization point, then time measurement can be performed, but the process becomes complicated and errors in matching detection reduce accuracy
Solution Approach 1:
The patent extracts the phase synchronization function from the time-to-digital conversion process itself and implements it separately using dedicated PLL circuits. This separation removes the complexity of edge matching detection from the conversion process, simplifying the overall system while maintaining high accuracy through dedicated synchronization hardware
Solution Approach 2:
The patent replaces the mechanical edge matching detection method with an electronic phase synchronization system using PLL circuits. This substitution eliminates the complexity and error-prone nature of detecting edge coincidences, replacing it with a more robust electronic phase-locking mechanism that maintains accuracy while simplifying the conversion process
3Productivity
If phase synchronization is performed using a single PLL circuit, then device complexity is reduced, but the frequency of phase synchronization decreases
Solution Approach 1:
The patent segments the phase synchronization task into two independent PLL circuits, each handling one clock signal separately. This segmentation allows both PLL circuits to operate simultaneously at high frequencies, increasing the overall phase synchronization frequency compared to a single PLL circuit that would need to handle both signals sequentially or manage complex multi-signal synchronization
Data Source
AI summary
A circuit device includes a first PLL circuit to which a first clock signal having a first clock frequency generated using a first resonator and a reference clock signal are input, and which performs phase synchronization between the first clock signal and the reference clock signal, a second PLL circuit to which a second clock signal generated using a second resonator and having a second clock frequency different from the first clock frequency and the reference clock signal are input, and which performs phase synchronization between the second clock signal and the reference clock signal, and a time-to-digital conversion circuit adapted to convert time into a digital value using the first clock signal and the second clock signal.