Dual-PLL Active Converter Control for VSD Line Dropout Sync
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Solution Overview
Problem
Variable speed drives (VSDs) with active converters generate high common mode voltage, leading to premature bearing failures and harmonic distortion, and struggle with maintaining synchronous operation during power outages and resynchronization.
Innovation Solution
A VSD system with a converter stage, DC link, and inverter stage, incorporating phase angle tracking using two Phase-Locked-Loops (PLLs) and an integral bypass Active Converter configuration, along with a liquid- or refrigerant-cooled inductor, to reduce common mode and differential mode voltage stress and improve power factor correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If active converter technology is used to provide power factor correction and reduced input current harmonics, then power factor and harmonic distortion are improved, but common mode voltage increases causing bearing fluting and premature bearing failures
Solution Approach 1:
A common mode choke is introduced as an intermediary component in the active converter circuit to suppress common mode voltage. The choke acts as a mediator that blocks common mode currents while allowing differential mode power transmission, thereby reducing bearing fluting and premature bearing failures while maintaining power factor correction benefits
Solution Approach 2:
The patent modifies operating parameters of the active converter including switching frequencies, pulse width modulation duty cycles, and filter component values to optimize the balance between power factor correction performance and common mode voltage generation. By adjusting these parameters, the system achieves improved power factor while minimizing harmful common mode effects
2Reliability
If the VSD is required to ride-through an extended loss of input line-to-line voltage and resynchronize, then reliability during power outages is improved, but the ability to retain d-q reference frame angle and quickly lock back onto mains becomes compromised
Solution Approach 1:
The system performs preliminary actions by continuously tracking and storing phase angle information in memory even before power outages occur. During normal operation, the Phase-Locked-Loop continuously updates the reference frame angle, and this information is preserved in non-volatile memory or held in capacitors, enabling the system to quickly resume synchronous operation without losing phase angle knowledge when power is restored
Solution Approach 2:
A feedback mechanism using Phase-Locked-Loop circuitry continuously monitors the input mains voltage phase angle and adjusts the d-q reference frame accordingly. This feedback system ensures that even during extended power outages, the system maintains accurate phase angle tracking capability and can quickly resynchronize when power is restored, preventing loss of synchronization information
3Speed
If a filter with high cutoff frequency and small integrating capacitor is used in the Phase-Locked-Loop, then response speed is improved, but filtering effectiveness may be reduced
Solution Approach 1:
The patent implements a dynamic filter design where the Phase-Locked-Loop filter characteristics are adaptively adjusted based on operating conditions. The filter cutoff frequency and integrating capacitor values are optimized to provide fast response during normal operation while maintaining adequate filtering effectiveness. The system dynamically balances between speed and filtering by adjusting loop bandwidth and filter parameters according to the specific operational state
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3
AI summary
Systems and methods for synchronous operation of variable speed drives having active converters include extending the synchronous operation of an active converter to the AC mains voltage during complete line dropout. A phase angle control circuit includes a squaring amplifier, a first phase-lock loop circuit associated and a second phase-lock loop circuit. The squaring amplifier receives the AC power source and outputs a rectangular output signal to a pair of phase lock loop (PLL) circuits. The first PLL circuit with a first lag-lead filter is configured with a high cutoff frequency to provide the converter stage with a phase angle parameter; and the second phase-lock loop circuit including a second lag-lead filter configured to have a low cutoff frequency to provide the lag-lead filter the capability of storing the phase angle of the mains voltage during mains interruption.